diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 676d7a7..29910ca 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -80,17 +80,6 @@
     delete reset;
 }
 
-template <class CPU>
-void
-zeroRegisters(CPU *cpu)
-{
-    // Insure ISA semantics
-    // (no longer very clean due to the change in setIntReg() in the
-    // cpu model.  Consider changing later.)
-    cpu->thread->setIntReg(ZeroReg, 0);
-    cpu->thread->setFloatReg(ZeroReg, 0);
-}
-
 ////////////////////////////////////////////////////////////////////////
 //
 //
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index bf585fd..46af121 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -58,13 +58,6 @@
     return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 // Alpha IPR register accessors
 inline bool PcPAL(Addr addr) { return addr & 0x3; }
 inline void startupCPU(ThreadContext *tc, int cpuId)
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 4d1348a..538c831 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -95,13 +95,6 @@
     }
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 inline void startupCPU(ThreadContext *tc, int cpuId)
 {
     tc->activate();
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 495845d..24c451d 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -217,17 +217,6 @@
     }
 }
 
-template <class CPU>
-void
-zeroRegisters(CPU *cpu)
-{
-    // Insure ISA semantics
-    // (no longer very clean due to the change in setIntReg() in the
-    // cpu model.  Consider changing later.)
-    cpu->thread->setIntReg(ZeroReg, 0);
-    cpu->thread->setFloatReg(ZeroReg, 0);
-}
-
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index dde386c..0cd066f 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -87,9 +87,6 @@
     }
 }
 
-template <class CPU>
-void zeroRegisters(CPU *cpu);
-
 ////////////////////////////////////////////////////////////////////////
 //
 //  Translation stuff
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 1a13d1e..b41533e 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -49,13 +49,6 @@
     return retPC;
 }
 
-/**
- * Function to ensure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 inline void
 startupCPU(ThreadContext *tc, int cpuId)
 {
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index ae57996..48476cb 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -62,13 +62,6 @@
     return !(pstate.priv || hpstate.hpriv);
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 void initCPU(ThreadContext *tc, int cpuId);
 
 inline void
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 87d5cbb..c88a4c7 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -69,13 +69,6 @@
         }
     }
 
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param tc The thread context.
-     */
-    template <class TC>
-    void zeroRegisters(TC *tc);
-
     void initCPU(ThreadContext *tc, int cpuId);
 
     void startupCPU(ThreadContext *tc, int cpuId);