)]}' { "commit": "144ce7f12c13998d28cfad67db99052c672f3dd0", "tree": "aae6ef025eae77483d813d9b9c809f1a9366ab26", "parents": [ "7b16b17e619490685edb875cd9678fc2fb1943e9" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Sun Oct 30 11:48:56 2022 -0700" }, "committer": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Mon Oct 31 14:40:30 2022 +0000" }, "message": "dev-amdgpu: Fix GART PTE size\n\nThe GART table is a legacy 1-level page table primarily used for\nsupervisor mode accesses to GPUs. The PTE size is 64-bits, not 32-bit.\nThis causes memory sizes \u003e3GB (in X86) to fail loading amdgpu driver.\n\nThis changeset fixes the issue by setting the GART mappings to the\ncorrect data type.\n\nChange-Id: Ibfba2443675fe28316d26afa5f1a14885fdce40c\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65091\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "227e69ec1576429272b1e4f5e90fc56f6cd47505", "old_mode": 33188, "old_path": "src/dev/amdgpu/amdgpu_device.cc", "new_id": "2b58b200ea63d0d3955d97021ed14d5b421b72d8", "new_mode": 33188, "new_path": "src/dev/amdgpu/amdgpu_device.cc" }, { "type": "modify", "old_id": "8df169b79a506ed1396c21e0ae9571baec4adb54", "old_mode": 33188, "old_path": "src/dev/amdgpu/amdgpu_vm.hh", "new_id": "212a688716ecb927caed1d29774a1fca7be337d1", "new_mode": 33188, "new_path": "src/dev/amdgpu/amdgpu_vm.hh" } ] }