diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py
index 4507768..11d52c0 100644
--- a/configs/example/hmc_hello.py
+++ b/configs/example/hmc_hello.py
@@ -49,7 +49,7 @@
 system = System()
 # use timing mode for the interaction between requestor-responder ports
 system.mem_mode = 'timing'
-# set the clock fequency of the system
+# set the clock frequency of the system
 clk = '1GHz'
 vd = VoltageDomain(voltage='1V')
 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
diff --git a/configs/example/hmctest.py b/configs/example/hmctest.py
index f4c0a2c..429ea4a 100644
--- a/configs/example/hmctest.py
+++ b/configs/example/hmctest.py
@@ -50,7 +50,7 @@
     system = System()
     # use timing mode for the interaction between requestor-responder ports
     system.mem_mode = 'timing'
-    # set the clock fequency of the system
+    # set the clock frequency of the system
     clk = '100GHz'
     vd = VoltageDomain(voltage='1V')
     system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py
index 235165b..7810c3d 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -43,7 +43,7 @@
 # create the system we are going to simulate
 system = System()
 
-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py
index 591be0c..7a7956c 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -70,7 +70,7 @@
 # create the system we are going to simulate
 system = System()
 
-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part2/simple_cache.py b/configs/learning_gem5/part2/simple_cache.py
index adda386..dc3a162 100644
--- a/configs/learning_gem5/part2/simple_cache.py
+++ b/configs/learning_gem5/part2/simple_cache.py
@@ -39,7 +39,7 @@
 # create the system we are going to simulate
 system = System()
 
-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part2/simple_memobj.py b/configs/learning_gem5/part2/simple_memobj.py
index 49b0846..eaceae9 100644
--- a/configs/learning_gem5/part2/simple_memobj.py
+++ b/configs/learning_gem5/part2/simple_memobj.py
@@ -39,7 +39,7 @@
 # create the system we are going to simulate
 system = System()
 
-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part3/ruby_test.py b/configs/learning_gem5/part3/ruby_test.py
index d0c3910..05096ec 100644
--- a/configs/learning_gem5/part3/ruby_test.py
+++ b/configs/learning_gem5/part3/ruby_test.py
@@ -44,7 +44,7 @@
 # create the system we are going to simulate
 system = System()
 
-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part3/simple_ruby.py b/configs/learning_gem5/part3/simple_ruby.py
index 2e65ebd..3d9fe9a 100644
--- a/configs/learning_gem5/part3/simple_ruby.py
+++ b/configs/learning_gem5/part3/simple_ruby.py
@@ -53,7 +53,7 @@
 # create the system we are going to simulate
 system = System()
 
-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()