src/arch/x86/emulenv.cc

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#include "arch/x86/emulenv.hh"

#include <cassert>

#include "base/logging.hh"

namespace gem5
{

using namespace X86ISA;

void EmulEnv::doModRM(const ExtMachInst & machInst)
{
    assert(machInst.modRM.mod != 3);
    //Use the SIB byte for addressing if the modrm byte calls for it.
    if (machInst.modRM.rm == 4 && machInst.addrSize != 2) {
        scale = 1 << machInst.sib.scale;
        index = RegId(IntRegClass, machInst.sib.index | (machInst.rex.x << 3));
        base = RegId(IntRegClass, machInst.sib.base | (machInst.rex.b << 3));
        //In this special case, we don't use a base. The displacement also
        //changes, but that's managed by the decoder.
        if (machInst.sib.base == (RegIndex)int_reg::Rbp &&
                machInst.modRM.mod == 0)
            base = int_reg::T0;
        //In -this- special case, we don't use an index.
        if (index == int_reg::Rsp)
            index = int_reg::T0;
    } else {
        if (machInst.addrSize == 2) {
            unsigned rm = machInst.modRM.rm;
            if (rm <= 3) {
                scale = 1;
                if (rm < 2) {
                    base = int_reg::Rbx;
                } else {
                    base = int_reg::Rbp;
                }
                index = RegId(IntRegClass,
                        (rm % 2) ? int_reg::Rdi : int_reg::Rsi);
            } else {
                scale = 0;
                switch (rm) {
                  case 4:
                    base = int_reg::Rsi;
                    break;
                  case 5:
                    base = int_reg::Rdi;
                    break;
                  case 6:
                    // There is a special case when mod is 0 and rm is 6.
                    base = machInst.modRM.mod == 0 ? int_reg::T0 :
                        int_reg::Rbp;
                    break;
                  case 7:
                    base = int_reg::Rbx;
                    break;
                }
            }
        } else {
            scale = 0;
            base = RegId(IntRegClass,
                    machInst.modRM.rm | (machInst.rex.b << 3));
            if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
                //Since we need to use a different encoding of this
                //instruction anyway, just ignore the base in those cases
                base = int_reg::T0;
            }
        }
    }
    //Figure out what segment to use.
    if (base != int_reg::Rbp && base != int_reg::Rsp) {
        seg = SEGMENT_REG_DS;
    } else {
        seg = SEGMENT_REG_SS;
    }
    //Handle any segment override that might have been in the instruction
    int segFromInst = machInst.legacy.seg;
    if (segFromInst)
        seg = (SegmentRegIndex)(segFromInst - 1);
}

void EmulEnv::setSeg(const ExtMachInst & machInst)
{
    seg = SEGMENT_REG_DS;
    //Handle any segment override that might have been in the instruction
    int segFromInst = machInst.legacy.seg;
    if (segFromInst)
        seg = (SegmentRegIndex)(segFromInst - 1);
}

} // namespace gem5