tree 8ab1d22fcfbc158dafc1a9e92a5d7562c820dc95
parent 7e19b26f503435f07dc4b5675061facc521b8c91
author Adrian Herrera <adrian.herrera@arm.com> 1573226721 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1574089261 +0000

arch-arm: R/W interface to AArch32 HCR2 misc reg

This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.

Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>