# -*- mode:python -*-

# Copyright (c) 2009, 2012-2013, 2017-2018, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2007-2008 The Florida State University
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Import('*')

GTest('aapcs64.test', 'aapcs64.test.cc', '../../base/debug.cc')
Source('decoder.cc', tags='arm isa')
Source('faults.cc', tags='arm isa')
Source('htm.cc', tags='arm isa')
Source('insts/branch.cc', tags='arm isa')
Source('insts/branch64.cc', tags='arm isa')
Source('insts/data64.cc', tags='arm isa')
Source('insts/macromem.cc', tags='arm isa')
Source('insts/mem.cc', tags='arm isa')
Source('insts/mem64.cc', tags='arm isa')
Source('insts/misc.cc', tags='arm isa')
Source('insts/misc64.cc', tags='arm isa')
Source('insts/pred_inst.cc', tags='arm isa')
Source('insts/pseudo.cc', tags='arm isa')
Source('insts/static_inst.cc', tags='arm isa')
Source('insts/sve.cc', tags='arm isa')
Source('insts/sve_mem.cc', tags='arm isa')
Source('insts/vfp.cc', tags='arm isa')
Source('insts/fplib.cc', tags='arm isa')
Source('insts/crypto.cc', tags='arm isa')
Source('insts/tme64.cc', tags='arm isa')
if env['PROTOCOL'] == 'MESI_Three_Level_HTM':
    Source('insts/tme64ruby.cc', tags='arm isa')
else:
    Source('insts/tme64classic.cc', tags='arm isa')
Source('interrupts.cc', tags='arm isa')
Source('isa.cc', tags='arm isa')
Source('isa_device.cc', tags='arm isa')
Source('linux/process.cc', tags='arm isa')
Source('linux/se_workload.cc', tags='arm isa')
Source('linux/fs_workload.cc', tags='arm isa')
Source('freebsd/fs_workload.cc', tags='arm isa')
Source('freebsd/se_workload.cc', tags='arm isa')
Source('fs_workload.cc', tags='arm isa')
Source('regs/misc.cc', tags='arm isa')
Source('mmu.cc', tags='arm isa')
Source('nativetrace.cc', tags='arm isa')
Source('pagetable.cc', tags='arm isa')
Source('pauth_helpers.cc', tags='arm isa')
Source('pmu.cc', tags='arm isa')
Source('process.cc', tags='arm isa')
Source('qarma.cc', tags='arm isa')
Source('remote_gdb.cc', tags='arm isa')
Source('reg_abi.cc', tags='arm isa')
Source('semihosting.cc', tags='arm isa')
Source('system.cc', tags='arm isa')
Source('table_walker.cc', tags='arm isa')
Source('self_debug.cc', tags='arm isa')
Source('stage2_lookup.cc', tags='arm isa')
Source('tlb.cc', tags='arm isa')
Source('tlbi_op.cc', tags='arm isa')
Source('utility.cc', tags='arm isa')

SimObject('ArmDecoder.py', sim_objects=['ArmDecoder'], tags='arm isa')
SimObject('ArmFsWorkload.py', sim_objects=[
    'ArmFsWorkload', 'ArmFsLinux', 'ArmFsFreebsd'],
    enums=['ArmMachineType'], tags='arm isa')
SimObject('ArmInterrupts.py', sim_objects=['ArmInterrupts'], tags='arm isa')
SimObject('ArmISA.py', sim_objects=['ArmISA'], enums=['DecoderFlavor'],
    tags='arm isa')
SimObject('ArmMMU.py', sim_objects=['ArmTableWalker', 'ArmMMU'],
    tags='arm isa')
SimObject('ArmNativeTrace.py', sim_objects=['ArmNativeTrace'], tags='arm isa')
SimObject('ArmSemihosting.py', sim_objects=['ArmSemihosting'], tags='arm isa')
SimObject('ArmSeWorkload.py', sim_objects=[
    'ArmSEWorkload', 'ArmEmuLinux', 'ArmEmuFreebsd'], tags='arm isa')
SimObject('ArmSystem.py', sim_objects=['ArmSystem', 'ArmRelease'],
    enums=['ArmExtension'], tags='arm isa')
SimObject('ArmTLB.py', sim_objects=['ArmTLB'], enums=['ArmLookupLevel'],
    tags='arm isa')
SimObject('ArmPMU.py', sim_objects=['ArmPMU'], tags='arm isa')

DebugFlag('Arm', tags='arm isa')
DebugFlag('ArmTme', 'Transactional Memory Extension', tags='arm isa')
DebugFlag('Semihosting', tags='arm isa')
DebugFlag('PMUVerbose', "Performance Monitor", tags='arm isa')

# Add files generated by the ISA description.
ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6, tags='arm isa')