src/mem/ruby/slicc_interface/Controller.py

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from m5.params import *
from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject

class RubyController(ClockedObject):
    type = 'RubyController'
    cxx_class = 'gem5::ruby::AbstractController'
    cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
    abstract = True

    version = Param.Int("")
    addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this "
                                        "controller responds to")
    cluster_id = Param.UInt32(0, "Id of this controller's cluster")

    transitions_per_cycle = \
        Param.Int(32, "no. of  SLICC state machine transitions per cycle")
    buffer_size = Param.UInt32(0, "max buffer size 0 means infinite")

    recycle_latency = Param.Cycles(10, "")
    number_of_TBEs = Param.Int(256, "")
    ruby_system = Param.RubySystem("")

    # This is typically a proxy to the icache/dcache hit latency.
    # If the latency depends on the request type or protocol-specific states,
    # the protocol may ignore this parameter by overriding the
    # mandatoryQueueLatency function
    mandatory_queue_latency = \
        Param.Cycles(1, "Default latency for requests added to the " \
                        "mandatory queue on top-level controllers")

    memory_out_port = RequestPort("Port for attaching a memory controller")
    memory = DeprecatedParam(memory_out_port, "The request port for Ruby "
        "memory output to the main memory is now called `memory_out_port`")

    system = Param.System(Parent.any, "system object parameter")

    # These can be used by a protocol to enable reuse of the same machine
    # types to model different levels of the cache hierarchy
    downstream_destinations = VectorParam.RubyController([],
                    "Possible destinations for requests sent towards memory")