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# Copyright 2019 Google, Inc.
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from m5.params import *
from m5.proxy import *

from m5.objects.BaseCPU import BaseCPU
from m5.objects.BaseInterrupts import BaseInterrupts
from m5.objects.BaseISA import BaseISA
from m5.objects.BaseTLB import BaseTLB
from m5.objects.BaseMMU import BaseMMU

class IrisTLB(BaseTLB):
    type = 'IrisTLB'
    cxx_class = 'gem5::Iris::TLB'
    cxx_header = 'arch/arm/fastmodel/iris/tlb.hh'

class IrisMMU(BaseMMU):
    type = 'IrisMMU'
    cxx_class = 'gem5::Iris::MMU'
    cxx_header = 'arch/arm/fastmodel/iris/mmu.hh'
    itb = IrisTLB(entry_type="instruction")
    dtb = IrisTLB(entry_type="data")

class IrisInterrupts(BaseInterrupts):
    type = 'IrisInterrupts'
    cxx_class = 'gem5::Iris::Interrupts'
    cxx_header = 'arch/arm/fastmodel/iris/interrupts.hh'

class IrisISA(BaseISA):
    type = 'IrisISA'
    cxx_class = 'gem5::Iris::ISA'
    cxx_header = 'arch/arm/fastmodel/iris/isa.hh'

class IrisCPU():
    ArchMMU = IrisMMU
    ArchInterrupts = IrisInterrupts
    ArchISA = IrisISA

class IrisBaseCPU(BaseCPU, IrisCPU):
    type = 'IrisBaseCPU'
    abstract = True
    cxx_class = 'gem5::Iris::BaseCPU'
    cxx_header = 'arch/arm/fastmodel/iris/cpu.hh'

    @classmethod
    def memory_mode(cls):
        return 'atomic_noncaching'

    @classmethod
    def require_caches(cls):
        return False

    @classmethod
    def support_take_over(cls):
        #TODO Make this work.
        return False

    evs = Param.SystemC_ScModule(
            "Fast model exported virtual subsystem holding cores")
    thread_paths = VectorParam.String(
            "Sub-paths to elements in the EVS which support a thread context")

    mmu = IrisMMU()

    def createThreads(self):
        if len(self.isa) == 0:
            self.isa = [ IrisISA() for i in range(self.numThreads) ]
        else:
            assert(len(self.isa) == int(self.numThreads))