commit 20ed09d1a1013f0656684173ff65ba8f85c9555c
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Dec 04 14:16:47 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Feb 10 09:41:11 2020 +0000
tree 4219354a6087c3d99df907722c7da8de16394894
parent 6a4d111855318a054da9525948879e8081e76cc1

arch-arm: LDTRSW was not marked as unpriviledged

Change-Id: If0f2b835e40ef011eba884b1dcd81f14531fd1ce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24043
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

src/arch/arm/isa/insts/ldr64.isa

diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index d6e4f5a..16c0d93 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2014, 2017 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -436,7 +436,7 @@
     LoadImm64("ldtrh", "LDTRH64_IMM", 2, False, True).emit()
     LoadImm64("ldtrsh", "LDTRSHW64_IMM", 2, True, True).emit()
     LoadImm64("ldtrsh", "LDTRSHX64_IMM", 2, True, True, flavor="widen").emit()
-    LoadImm64("ldtrsw", "LDTRSW64_IMM", 4, True, flavor="widen").emit()
+    LoadImm64("ldtrsw", "LDTRSW64_IMM", 4, True, True, flavor="widen").emit()
     LoadImm64("ldtr", "LDTRW64_IMM", 4, False, True).emit()
     LoadImm64("ldtr", "LDTRX64_IMM", 8, False, True).emit()