blob: 7a02630d287ca7b8691bd26ed5c54fc9b84bb406 [file] [log] [blame]
# -*- coding: utf-8 -*-
# Copyright (c) 2017 Jason Lowe-Power
# All rights reserved.
#
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# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
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# neither the name of the copyright holders nor the names of its
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# Authors: Jason Lowe-Power
from m5.params import *
from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject
class SimpleCache(ClockedObject):
type = 'SimpleCache'
cxx_header = "learning_gem5/part2/simple_cache.hh"
# Vector port example. Both the instruction and data ports connect to this
# port which is automatically split out into two ports.
cpu_side = VectorSlavePort("CPU side port, receives requests")
mem_side = MasterPort("Memory side port, sends requests")
latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")
size = Param.MemorySize('16kB', "The size of the cache")
system = Param.System(Parent.any, "The system this cache is part of")