arch-arm: Additional bits in misc ARM registers to use with the TLB and page walker
Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd
Reviewed-on: https://gem5-review.googlesource.com/c/14555
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index c3ee6ca..f668d9b 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -460,6 +460,7 @@
Bitfield<5> pd1;
// Long-descriptor translation table format
Bitfield<2, 0> t0sz;
+ Bitfield<6> t2e;
Bitfield<7> epd0;
Bitfield<9, 8> irgn0;
Bitfield<11, 10> orgn0;
@@ -481,6 +482,8 @@
// TCR_EL2/3 (AArch64)
Bitfield<18, 16> ps;
Bitfield<20> tbi;
+ Bitfield<41> hpd0;
+ Bitfield<42> hpd1;
EndBitUnion(TTBCR)
// Fields of TCR_EL{1,2,3} (mostly overlapping)
@@ -505,6 +508,10 @@
Bitfield<36> as; // EL1
Bitfield<37> tbi0; // EL1
Bitfield<38> tbi1; // EL1
+ Bitfield<39> ha;
+ Bitfield<40> hd;
+ Bitfield<41> hpd0;
+ Bitfield<42> hpd1;
EndBitUnion(TCR)
BitUnion32(HTCR)
@@ -512,6 +519,7 @@
Bitfield<9, 8> irgn0;
Bitfield<11, 10> orgn0;
Bitfield<13, 12> sh0;
+ Bitfield<24> hpd;
EndBitUnion(HTCR)
BitUnion32(VTCR_t)
@@ -524,6 +532,8 @@
Bitfield<13, 12> sh0;
Bitfield<15, 14> tg0;
Bitfield<18, 16> ps; // Only defined for VTCR_EL2
+ Bitfield<21> ha; // Only defined for VTCR_EL2
+ Bitfield<22> hd; // Only defined for VTCR_EL2
EndBitUnion(VTCR_t)
BitUnion32(PRRR)
