tree 53c45e11ba848bc587e65f636ae18c98ff502486
parent 791092663183bcf01468ca84b6d3c177f0cf7fc7
author Cui Jin <cuijinbird@gmail.com> 1640099703 +0800
committer Jin Cui <cuijinbird@gmail.com> 1640217110 +0000

arch-riscv: rvc instruction is mistaken as branch

Fetch in O3CPU mistakes the normal non-branching compressed
instructions, and regards it as a branch. This issue interrupts
the consecutive instruction stream, thus affecting performance
of cpu front-end.
This fix sets the compressed for PCState during decoding.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1137

Change-Id: I7607d563bba8a08869e104877fc3c11c94cbe904
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54644
Reviewed-by: Jin Cui <cuijinbird@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>