tree 6c56cf7fe978a9b922fa6bcaf0b9523a7e7b8701
parent 6f3f6c16f3bdd5333eec157cd6db88199deab5fc
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1669192550 +0000
committer Bobby Bruce <bbruce@ucdavis.edu> 1670271933 +0000

arch-arm: Setup TC/ISA at construction time 2nd attempt

This partly reverts commit ec75787aef56665e893d70293bf3a0f93c33bb6a
by fixing the original problem noted by Bobby (long regressions):

setupThreadContext has to be implemented otherswise the GICv3 cpu interface
will end up holding old references when switching TC/ISAs.

This new implementation is still setting up the cpu interface reference
in the ISA only when it is required, but it is storing the
TC/ISA reference within the interface every time the ISA::setupThreadContext
gets called.

Change-Id: I2f54f95761d63655162c253e887b872f3718c764
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66291
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>