src/arch/amdgpu/vega/insts/gpu_static_inst.hh

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#ifndef __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
#define __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__

#include "arch/amdgpu/vega/gpu_registers.hh"
#include "arch/amdgpu/vega/operand.hh"
#include "gpu-compute/gpu_static_inst.hh"
#include "gpu-compute/scalar_register_file.hh"
#include "gpu-compute/vector_register_file.hh"
#include "gpu-compute/wavefront.hh"

namespace gem5
{

namespace VegaISA
{
    class VEGAGPUStaticInst : public GPUStaticInst
    {
      public:
        VEGAGPUStaticInst(const std::string &opcode);
        ~VEGAGPUStaticInst();

        void generateDisassembly() override { disassembly = _opcode; }

        bool
        isFlatScratchRegister(int opIdx) override
        {
            return isFlatScratchReg(opIdx);
        }

        bool
        isExecMaskRegister(int opIdx) override
        {
            return isExecMask(opIdx);
        }

        void initOperandInfo() override { return; }
        int getOperandSize(int opIdx) override { return 0; }

        /**
          * Return the number of tokens needed by the coalescer. In VEGA there
          * is generally one packet per memory request per lane generated. In
          * HSAIL, the number of dest operands is used for loads and src
          * operands for stores. This method should be overriden on a per-inst
          * basis when this value differs.
          */
        int coalescerTokenCount() const override { return 1; }
        ScalarRegU32 srcLiteral() const override { return _srcLiteral; }

      protected:
        void panicUnimplemented() const;

        /**
         * if the instruction has a src literal - an immediate
         * value that is part of the instruction stream - we
         * store that here
         */
        ScalarRegU32 _srcLiteral;
    }; // class VEGAGPUStaticInst

} // namespace VegaISA
} // namespace gem5

#endif //__ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__