# -*- mode:python -*-

# Copyright (c) 2016 RISC-V Foundation
# Copyright (c) 2016 The University of Virginia
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#
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# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
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# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
#
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from m5.params import *

from m5.objects.System import System
from m5.objects.Workload import Workload, KernelWorkload

class RiscvBareMetal(Workload):
    type = 'RiscvBareMetal'
    cxx_class = 'gem5::RiscvISA::BareMetal'
    cxx_header = 'arch/riscv/bare_metal/fs_workload.hh'

    bootloader = Param.String("File, that contains the bootloader code")
    bare_metal = Param.Bool(True, "Using Bare Metal Application?")
    reset_vect = Param.Addr(0x0, 'Reset vector')

class RiscvLinux(KernelWorkload):
    type = 'RiscvLinux'
    cxx_class = 'gem5::RiscvISA::FsLinux'
    cxx_header = 'arch/riscv/linux/fs_workload.hh'

    dtb_filename = Param.String("",
        "File that contains the Device Tree Blob. Don't use DTB if empty.")
    dtb_addr = Param.Addr(0x87e00000, "DTB address")