| commit | 25b4defa6aff3873e283c54615cda214786b5db7 | [log] [tgz] |
|---|---|---|
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | Mon Dec 19 16:00:34 2022 +0000 |
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | Tue Dec 27 12:11:05 2022 +0000 |
| tree | f0e8cb14504376986edb28c37bd0cd5b18a11995 | |
| parent | 8d117aad71283601c6ceb7145817df1557c3bdfd [diff] |
util: Fix missing include of sim/core.hh in util-tlm Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66852 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>