25d36c81c91b5504d3192cd307ce855a7f8025a8 - public/gem5

commit	25d36c81c91b5504d3192cd307ce855a7f8025a8	[log] [tgz]
author	Gabe Black <gabe.black@gmail.com>	Mon Oct 25 04:08:04 2021 -0700
committer	Gabe Black <gabe.black@gmail.com>	Mon Dec 06 03:09:22 2021 +0000
tree	88779b8842032566b48c8729c7c4e06f97a130a4
parent	3e766837b05074e77b1f4eb49b7a832b55ada67f [diff]

arch,cpu: Turn the Decoder objects into SimObjects.

Change-Id: I85839880db588b3b92064b8fcbf053c1811a1fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/ArmDecoder.py[Added - diff]
src/arch/arm/SConscript[diff]
src/arch/arm/decoder.cc[diff]
src/arch/arm/decoder.hh[diff]
src/arch/generic/InstDecoder.py[Added - diff]
src/arch/generic/SConscript[diff]
src/arch/generic/decoder.hh[diff]
src/arch/mips/MipsDecoder.py[Added - diff]
src/arch/mips/SConscript[diff]
src/arch/mips/decoder.hh[diff]
src/arch/power/PowerDecoder.py[Added - diff]
src/arch/power/SConscript[diff]
src/arch/power/decoder.hh[diff]
src/arch/riscv/RiscvDecoder.py[Added - diff]
src/arch/riscv/SConscript[diff]
src/arch/riscv/decoder.hh[diff]
src/arch/sparc/SConscript[diff]
src/arch/sparc/SparcDecoder.py[Added - diff]
src/arch/sparc/decoder.hh[diff]
src/arch/x86/SConscript[diff]
src/arch/x86/X86Decoder.py[Added - diff]
src/arch/x86/decoder.hh[diff]
src/cpu/BaseCPU.py[diff]
src/cpu/checker/cpu.cc[diff]
src/cpu/kvm/base.cc[diff]
src/cpu/minor/cpu.cc[diff]
src/cpu/o3/fetch.cc[diff]
src/cpu/simple/base.cc[diff]
src/cpu/simple_thread.cc[diff]
src/cpu/simple_thread.hh[diff]

30 files changed

tree: 88779b8842032566b48c8729c7c4e06f97a130a4