src/arch/riscv/isa/formats/fp.isa

// -*- mode:c++ -*-

// Copyright (c) 2015 Riscv Developers
// Copyright (c) 2016-2017 The University of Virginia
// Copyright (c) 2020 Barkhausen Institut
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//
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////////////////////////////////////////////////////////////////////
//
// Floating point operation instructions
//
def template FloatExecute {{
    Fault %(class_name)s::execute(ExecContext *xc,
        Trace::InstRecord *traceData) const
    {
        STATUS status = xc->readMiscReg(MISCREG_STATUS);
        if (status.fs == FPUStatus::OFF)
            return std::make_shared<IllegalInstFault>("FPU is off", machInst);

        %(op_decl)s;
        %(op_rd)s;

        RegVal FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
        std::feclearexcept(FE_ALL_EXCEPT);
        %(code)s;

        FFLAGS |= softfloat_exceptionFlags;
        softfloat_exceptionFlags = 0;
        xc->setMiscReg(MISCREG_FFLAGS, FFLAGS);

        %(op_wb)s;

        return NoFault;
    }
}};

def format FPROp(code, *opt_flags) {{
    iop = InstObjParams(name, Name, 'RegOp', code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = FloatExecute.subst(iop)
}};