tree a968701ca53eb7c987fd41ae53a2cc9fe125c9f2
parent c21a2a54ca366c2e699571b1dddd083a77601831
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1523959709 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1524139165 +0000

arch-arm: Add ARMv8.1 TTBR1_EL2 register

This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg
table, but stil leaving it unimplemented (Accessing it through MSR/MRS
causes an exception)

Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10063
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>