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/*
* Copyright (c) 2012, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/o3/thread_state.hh"
#include "cpu/o3/cpu.hh"
namespace gem5
{
namespace o3
{
ThreadState::ThreadState(CPU *_cpu, int _thread_num, Process *_process) :
gem5::ThreadState(_cpu, _thread_num, _process),
comInstEventQueue("instruction-based event queue")
{}
void
ThreadState::serialize(CheckpointOut &cp) const
{
gem5::ThreadState::serialize(cp);
// Use the ThreadContext serialization helper to serialize the
// TC.
gem5::serialize(*tc, cp);
}
void
ThreadState::unserialize(CheckpointIn &cp)
{
// Prevent squashing - we don't have any instructions in
// flight that we need to squash since we just instantiated a
// clean system.
noSquashFromTC = true;
gem5::ThreadState::unserialize(cp);
// Use the ThreadContext serialization helper to unserialize
// the TC.
gem5::unserialize(*tc, cp);
noSquashFromTC = false;
}
} // namespace o3
} // namespace gem5