tree 27e819a930c79dff6754de37062a0092ca9e798a
parent 1768c47bc4fc00e89601ad03c9091c9b949a6c97
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1566294514 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1567770808 +0000

arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs

The readMiscReg/setMiscReg methods were not forwarding register
reads/writes to the cpu interface when in AArch32.

Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>