commit 343f7b7bf667956cc0b62ff7ebdcdcc9363a5470
author Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Jun 28 14:20:49 2022 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Jul 05 08:45:01 2022 +0000
tree 4b34750f7903765ff464b9ea8455e07127eee86d
parent ea9620922c0f124f30432af792b245e9c96b5f41

arch-arm: Do not trap MISCREG_DC_ZVA_Xt to EL1 if in VHE host

Change-Id: I785be01fcb97b78e0b59f8f9a4f8d150208fa88a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60970
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/insts/misc64.cc

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 5bbb739..8d17a71 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013,2017-2021 Arm Limited
+ * Copyright (c) 2011-2013,2017-2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -135,7 +135,8 @@
       case MISCREG_DC_ZVA_Xt:
         // In syscall-emulation mode, this test is skipped and DCZVA is always
         // allowed at EL0
-        trap_to_sup =  el == EL0 && !sctlr.dze && FullSystem;
+        trap_to_sup =  el == EL0 && !(EL2Enabled(tc) && hcr.e2h && hcr.tge) &&
+            !sctlr.dze && FullSystem;
         break;
       case MISCREG_DC_CIVAC_Xt:
       case MISCREG_DC_CVAC_Xt: