| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.832017 |
| sim_ticks 832017490500 |
| final_tick 832017490500 |
| sim_freq 1000000000000 |
| host_inst_rate 917891 |
| host_op_rate 988888 |
| host_tick_rate 494444669 |
| host_mem_usage 271524 |
| host_seconds 1682.73 |
| sim_insts 1544563042 |
| sim_ops 1664032434 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 |
| system.physmem.bytes_read::cpu.inst 6178262360 |
| system.physmem.bytes_read::cpu.data 1581387671 |
| system.physmem.bytes_read::total 7759650031 |
| system.physmem.bytes_inst_read::cpu.inst 6178262360 |
| system.physmem.bytes_inst_read::total 6178262360 |
| system.physmem.bytes_written::cpu.data 624158392 |
| system.physmem.bytes_written::total 624158392 |
| system.physmem.num_reads::cpu.inst 1544565590 |
| system.physmem.num_reads::cpu.data 454909197 |
| system.physmem.num_reads::total 1999474787 |
| system.physmem.num_writes::cpu.data 172586108 |
| system.physmem.num_writes::total 172586108 |
| system.physmem.bw_read::cpu.inst 7425640002 |
| system.physmem.bw_read::cpu.data 1900666379 |
| system.physmem.bw_read::total 9326306381 |
| system.physmem.bw_inst_read::cpu.inst 7425640002 |
| system.physmem.bw_inst_read::total 7425640002 |
| system.physmem.bw_write::cpu.data 750174605 |
| system.physmem.bw_write::total 750174605 |
| system.physmem.bw_total::cpu.inst 7425640002 |
| system.physmem.bw_total::cpu.data 2650840984 |
| system.physmem.bw_total::total 10076480986 |
| system.pwrStateResidencyTicks::UNDEFINED 832017490500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 46 |
| system.cpu.pwrStateResidencyTicks::ON 832017490500 |
| system.cpu.numCycles 1664034982 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 1544563042 |
| system.cpu.committedOps 1664032434 |
| system.cpu.num_int_alu_accesses 1477900422 |
| system.cpu.num_fp_alu_accesses 36 |
| system.cpu.num_func_calls 27330256 |
| system.cpu.num_conditional_control_insts 167612489 |
| system.cpu.num_int_insts 1477900422 |
| system.cpu.num_fp_insts 36 |
| system.cpu.num_int_register_reads 2605402867 |
| system.cpu.num_int_register_writes 1125475224 |
| system.cpu.num_fp_register_reads 24 |
| system.cpu.num_fp_register_writes 16 |
| system.cpu.num_cc_register_reads 4992096239 |
| system.cpu.num_cc_register_writes 518236214 |
| system.cpu.num_mem_refs 633153380 |
| system.cpu.num_load_insts 458306334 |
| system.cpu.num_store_insts 174847046 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 1664034982 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 213462427 |
| system.cpu.op_class::No_OpClass 0 0.00% 0.00% |
| system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% |
| system.cpu.op_class::IntMult 700322 0.04% 61.95% |
| system.cpu.op_class::IntDiv 0 0.00% 61.95% |
| system.cpu.op_class::FloatAdd 0 0.00% 61.95% |
| system.cpu.op_class::FloatCmp 0 0.00% 61.95% |
| system.cpu.op_class::FloatCvt 0 0.00% 61.95% |
| system.cpu.op_class::FloatMult 0 0.00% 61.95% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% |
| system.cpu.op_class::FloatDiv 0 0.00% 61.95% |
| system.cpu.op_class::FloatMisc 0 0.00% 61.95% |
| system.cpu.op_class::FloatSqrt 0 0.00% 61.95% |
| system.cpu.op_class::SimdAdd 0 0.00% 61.95% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% |
| system.cpu.op_class::SimdAlu 0 0.00% 61.95% |
| system.cpu.op_class::SimdCmp 0 0.00% 61.95% |
| system.cpu.op_class::SimdCvt 0 0.00% 61.95% |
| system.cpu.op_class::SimdMisc 0 0.00% 61.95% |
| system.cpu.op_class::SimdMult 0 0.00% 61.95% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% |
| system.cpu.op_class::SimdShift 0 0.00% 61.95% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% |
| system.cpu.op_class::SimdSqrt 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% |
| system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% |
| system.cpu.op_class::MemRead 458306322 27.54% 89.49% |
| system.cpu.op_class::MemWrite 174847022 10.51% 100.00% |
| system.cpu.op_class::FloatMemRead 12 0.00% 100.00% |
| system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 1664032481 |
| system.membus.snoop_filter.tot_requests 0 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 |
| system.membus.trans_dist::ReadReq 1999474725 |
| system.membus.trans_dist::ReadResp 1999474786 |
| system.membus.trans_dist::WriteReq 172586047 |
| system.membus.trans_dist::WriteResp 172586047 |
| system.membus.trans_dist::SoftPFReq 1 |
| system.membus.trans_dist::SoftPFResp 1 |
| system.membus.trans_dist::LoadLockedReq 61 |
| system.membus.trans_dist::StoreCondReq 61 |
| system.membus.trans_dist::StoreCondResp 61 |
| system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 |
| system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 |
| system.membus.pkt_count::total 4344121790 |
| system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 |
| system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 |
| system.membus.pkt_size::total 8383808423 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 2172060895 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 2172060895 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 2172060895 |
| |
| ---------- End Simulation Statistics ---------- |
