commit 35763bdfb2550b74262e040e9cdf9f458ec3ecf4
author Yang Liu <numbksco@gmail.com> Tue Jan 17 13:57:23 2023 +0800
committer Bobby Bruce <bbruce@ucdavis.edu> Mon Jul 10 22:59:12 2023 +0000
tree 056f33990540554aaf0f6e1f42aecc00de57d038
parent eb07d3fcf4095aedda7faa50184c2228d5053ccd

arch: Add setRegOperand in VecRegOperand

VecRegOperand also need setRegOperand method to write back execution
result.

Change-Id: Ie50606014827c14a7219558dd003eb4747231649
Co-authored-by: Xuan Hu <huxuan@bosc.ac.cn>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67292
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/isa_parser/operand_types.py

diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py
index 174a54c..113cc2f 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -372,6 +372,7 @@
 
     def makeWrite(self):
         return f"""
+        xc->setRegOperand(this, {self.dest_reg_idx}, &tmp_d{self.dest_reg_idx});
         if (traceData) {{
             traceData->setData({self.reg_class}, &tmp_d{self.dest_reg_idx});
         }}