| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.230201 |
| sim_ticks 230201146500 |
| final_tick 230201146500 |
| sim_freq 1000000000000 |
| host_inst_rate 699032 |
| host_op_rate 736956 |
| host_tick_rate 936426495 |
| host_mem_usage 284812 |
| host_seconds 245.83 |
| sim_insts 171842484 |
| sim_ops 181165371 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.physmem.bytes_read::cpu.inst 110656 |
| system.physmem.bytes_read::cpu.data 110336 |
| system.physmem.bytes_read::total 220992 |
| system.physmem.bytes_inst_read::cpu.inst 110656 |
| system.physmem.bytes_inst_read::total 110656 |
| system.physmem.num_reads::cpu.inst 1729 |
| system.physmem.num_reads::cpu.data 1724 |
| system.physmem.num_reads::total 3453 |
| system.physmem.bw_read::cpu.inst 480693 |
| system.physmem.bw_read::cpu.data 479303 |
| system.physmem.bw_read::total 959995 |
| system.physmem.bw_inst_read::cpu.inst 480693 |
| system.physmem.bw_inst_read::total 480693 |
| system.physmem.bw_total::cpu.inst 480693 |
| system.physmem.bw_total::cpu.data 479303 |
| system.physmem.bw_total::total 959995 |
| system.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 400 |
| system.cpu.pwrStateResidencyTicks::ON 230201146500 |
| system.cpu.numCycles 460402293 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 171842484 |
| system.cpu.committedOps 181165371 |
| system.cpu.num_int_alu_accesses 143085668 |
| system.cpu.num_fp_alu_accesses 1752310 |
| system.cpu.num_func_calls 3545028 |
| system.cpu.num_conditional_control_insts 32201008 |
| system.cpu.num_int_insts 143085668 |
| system.cpu.num_fp_insts 1752310 |
| system.cpu.num_int_register_reads 238631773 |
| system.cpu.num_int_register_writes 98192342 |
| system.cpu.num_fp_register_reads 2822225 |
| system.cpu.num_fp_register_writes 2378039 |
| system.cpu.num_cc_register_reads 626384530 |
| system.cpu.num_cc_register_writes 190815535 |
| system.cpu.num_mem_refs 40540779 |
| system.cpu.num_load_insts 27896144 |
| system.cpu.num_store_insts 12644635 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 460402293 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 40300312 |
| system.cpu.op_class::No_OpClass 0 0.00% 0.00% |
| system.cpu.op_class::IntAlu 138988213 76.51% 76.51% |
| system.cpu.op_class::IntMult 908940 0.50% 77.01% |
| system.cpu.op_class::IntDiv 0 0.00% 77.01% |
| system.cpu.op_class::FloatAdd 0 0.00% 77.01% |
| system.cpu.op_class::FloatCmp 0 0.00% 77.01% |
| system.cpu.op_class::FloatCvt 0 0.00% 77.01% |
| system.cpu.op_class::FloatMult 0 0.00% 77.01% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% |
| system.cpu.op_class::FloatDiv 0 0.00% 77.01% |
| system.cpu.op_class::FloatMisc 0 0.00% 77.01% |
| system.cpu.op_class::FloatSqrt 0 0.00% 77.01% |
| system.cpu.op_class::SimdAdd 0 0.00% 77.01% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% |
| system.cpu.op_class::SimdAlu 0 0.00% 77.01% |
| system.cpu.op_class::SimdCmp 0 0.00% 77.01% |
| system.cpu.op_class::SimdCvt 0 0.00% 77.01% |
| system.cpu.op_class::SimdMisc 0 0.00% 77.01% |
| system.cpu.op_class::SimdMult 0 0.00% 77.01% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% |
| system.cpu.op_class::SimdShift 0 0.00% 77.01% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% |
| system.cpu.op_class::SimdSqrt 0 0.00% 77.01% |
| system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% |
| system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% |
| system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% |
| system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% |
| system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% |
| system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% |
| system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% |
| system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% |
| system.cpu.op_class::MemRead 27348059 15.06% 92.74% |
| system.cpu.op_class::MemWrite 12498389 6.88% 99.62% |
| system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% |
| system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 181650743 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.dcache.tags.replacements 40 |
| system.cpu.dcache.tags.tagsinuse 1363.564425 |
| system.cpu.dcache.tags.total_refs 40162626 |
| system.cpu.dcache.tags.sampled_refs 1789 |
| system.cpu.dcache.tags.avg_refs 22449.762996 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 1363.564425 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.332901 |
| system.cpu.dcache.tags.occ_percent::total 0.332901 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 |
| system.cpu.dcache.tags.tag_accesses 80330619 |
| system.cpu.dcache.tags.data_accesses 80330619 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.dcache.ReadReq_hits::cpu.data 27754163 |
| system.cpu.dcache.ReadReq_hits::total 27754163 |
| system.cpu.dcache.WriteReq_hits::cpu.data 12363187 |
| system.cpu.dcache.WriteReq_hits::total 12363187 |
| system.cpu.dcache.SoftPFReq_hits::cpu.data 462 |
| system.cpu.dcache.SoftPFReq_hits::total 462 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 |
| system.cpu.dcache.LoadLockedReq_hits::total 22407 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 |
| system.cpu.dcache.StoreCondReq_hits::total 22407 |
| system.cpu.dcache.demand_hits::cpu.data 40117350 |
| system.cpu.dcache.demand_hits::total 40117350 |
| system.cpu.dcache.overall_hits::cpu.data 40117812 |
| system.cpu.dcache.overall_hits::total 40117812 |
| system.cpu.dcache.ReadReq_misses::cpu.data 688 |
| system.cpu.dcache.ReadReq_misses::total 688 |
| system.cpu.dcache.WriteReq_misses::cpu.data 1100 |
| system.cpu.dcache.WriteReq_misses::total 1100 |
| system.cpu.dcache.SoftPFReq_misses::cpu.data 1 |
| system.cpu.dcache.SoftPFReq_misses::total 1 |
| system.cpu.dcache.demand_misses::cpu.data 1788 |
| system.cpu.dcache.demand_misses::total 1788 |
| system.cpu.dcache.overall_misses::cpu.data 1789 |
| system.cpu.dcache.overall_misses::total 1789 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 40571000 |
| system.cpu.dcache.ReadReq_miss_latency::total 40571000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 68930500 |
| system.cpu.dcache.WriteReq_miss_latency::total 68930500 |
| system.cpu.dcache.demand_miss_latency::cpu.data 109501500 |
| system.cpu.dcache.demand_miss_latency::total 109501500 |
| system.cpu.dcache.overall_miss_latency::cpu.data 109501500 |
| system.cpu.dcache.overall_miss_latency::total 109501500 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 |
| system.cpu.dcache.ReadReq_accesses::total 27754851 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 |
| system.cpu.dcache.WriteReq_accesses::total 12364287 |
| system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 |
| system.cpu.dcache.SoftPFReq_accesses::total 463 |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 |
| system.cpu.dcache.LoadLockedReq_accesses::total 22407 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 |
| system.cpu.dcache.StoreCondReq_accesses::total 22407 |
| system.cpu.dcache.demand_accesses::cpu.data 40119138 |
| system.cpu.dcache.demand_accesses::total 40119138 |
| system.cpu.dcache.overall_accesses::cpu.data 40119601 |
| system.cpu.dcache.overall_accesses::total 40119601 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.000025 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.000089 |
| system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 |
| system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 |
| system.cpu.dcache.demand_miss_rate::total 0.000045 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 |
| system.cpu.dcache.overall_miss_rate::total 0.000045 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664 |
| system.cpu.dcache.demand_avg_miss_latency::total 61242.449664 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881 |
| system.cpu.dcache.overall_avg_miss_latency::total 61208.216881 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu.dcache.writebacks::writebacks 16 |
| system.cpu.dcache.writebacks::total 16 |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 |
| system.cpu.dcache.ReadReq_mshr_misses::total 688 |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 |
| system.cpu.dcache.WriteReq_mshr_misses::total 1100 |
| system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 |
| system.cpu.dcache.SoftPFReq_mshr_misses::total 1 |
| system.cpu.dcache.demand_mshr_misses::cpu.data 1788 |
| system.cpu.dcache.demand_mshr_misses::total 1788 |
| system.cpu.dcache.overall_mshr_misses::cpu.data 1789 |
| system.cpu.dcache.overall_mshr_misses::total 1789 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39883000 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 39883000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67830500 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 67830500 |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 107713500 |
| system.cpu.dcache.demand_mshr_miss_latency::total 107713500 |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 107775500 |
| system.cpu.dcache.overall_mshr_miss_latency::total 107775500 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57969.476744 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57969.476744 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61664.090909 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61664.090909 |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60242.449664 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 60242.449664 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60243.432085 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 60243.432085 |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.icache.tags.replacements 1506 |
| system.cpu.icache.tags.tagsinuse 1147.953271 |
| system.cpu.icache.tags.total_refs 189857002 |
| system.cpu.icache.tags.sampled_refs 3051 |
| system.cpu.icache.tags.avg_refs 62227.794821 |
| system.cpu.icache.tags.warmup_cycle 0 |
| system.cpu.icache.tags.occ_blocks::cpu.inst 1147.953271 |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.560524 |
| system.cpu.icache.tags.occ_percent::total 0.560524 |
| system.cpu.icache.tags.occ_task_id_blocks::1024 1545 |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 24 |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 21 |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 288 |
| system.cpu.icache.tags.age_task_id_blocks_1024::3 270 |
| system.cpu.icache.tags.age_task_id_blocks_1024::4 942 |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 |
| system.cpu.icache.tags.tag_accesses 379723157 |
| system.cpu.icache.tags.data_accesses 379723157 |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230201146500 |
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| system.cpu.icache.ReadReq_hits::total 189857002 |
| system.cpu.icache.demand_hits::cpu.inst 189857002 |
| system.cpu.icache.demand_hits::total 189857002 |
| system.cpu.icache.overall_hits::cpu.inst 189857002 |
| system.cpu.icache.overall_hits::total 189857002 |
| system.cpu.icache.ReadReq_misses::cpu.inst 3051 |
| system.cpu.icache.ReadReq_misses::total 3051 |
| system.cpu.icache.demand_misses::cpu.inst 3051 |
| system.cpu.icache.demand_misses::total 3051 |
| system.cpu.icache.overall_misses::cpu.inst 3051 |
| system.cpu.icache.overall_misses::total 3051 |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 126321000 |
| system.cpu.icache.ReadReq_miss_latency::total 126321000 |
| system.cpu.icache.demand_miss_latency::cpu.inst 126321000 |
| system.cpu.icache.demand_miss_latency::total 126321000 |
| system.cpu.icache.overall_miss_latency::cpu.inst 126321000 |
| system.cpu.icache.overall_miss_latency::total 126321000 |
| system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 |
| system.cpu.icache.ReadReq_accesses::total 189860053 |
| system.cpu.icache.demand_accesses::cpu.inst 189860053 |
| system.cpu.icache.demand_accesses::total 189860053 |
| system.cpu.icache.overall_accesses::cpu.inst 189860053 |
| system.cpu.icache.overall_accesses::total 189860053 |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 |
| system.cpu.icache.ReadReq_miss_rate::total 0.000016 |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 |
| system.cpu.icache.demand_miss_rate::total 0.000016 |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 |
| system.cpu.icache.overall_miss_rate::total 0.000016 |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41403.146509 |
| system.cpu.icache.ReadReq_avg_miss_latency::total 41403.146509 |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 41403.146509 |
| system.cpu.icache.demand_avg_miss_latency::total 41403.146509 |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 41403.146509 |
| system.cpu.icache.overall_avg_miss_latency::total 41403.146509 |
| system.cpu.icache.blocked_cycles::no_mshrs 0 |
| system.cpu.icache.blocked_cycles::no_targets 0 |
| system.cpu.icache.blocked::no_mshrs 0 |
| system.cpu.icache.blocked::no_targets 0 |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.writebacks::writebacks 1506 |
| system.cpu.icache.writebacks::total 1506 |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 |
| system.cpu.icache.ReadReq_mshr_misses::total 3051 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 3051 |
| system.cpu.icache.demand_mshr_misses::total 3051 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 3051 |
| system.cpu.icache.overall_mshr_misses::total 3051 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123270000 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 123270000 |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123270000 |
| system.cpu.icache.demand_mshr_miss_latency::total 123270000 |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123270000 |
| system.cpu.icache.overall_mshr_miss_latency::total 123270000 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 |
| system.cpu.icache.demand_mshr_miss_rate::total 0.000016 |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 |
| system.cpu.icache.overall_mshr_miss_rate::total 0.000016 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40403.146509 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40403.146509 |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509 |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509 |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509 |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509 |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 2511.620011 |
| system.cpu.l2cache.tags.total_refs 2869 |
| system.cpu.l2cache.tags.sampled_refs 3453 |
| system.cpu.l2cache.tags.avg_refs 0.830872 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 1168.996513 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 1342.623498 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.040974 |
| system.cpu.l2cache.tags.occ_percent::total 0.076649 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 3453 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 341 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2517 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.105377 |
| system.cpu.l2cache.tags.tag_accesses 54029 |
| system.cpu.l2cache.tags.data_accesses 54029 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.l2cache.WritebackDirty_hits::writebacks 16 |
| system.cpu.l2cache.WritebackDirty_hits::total 16 |
| system.cpu.l2cache.WritebackClean_hits::writebacks 1448 |
| system.cpu.l2cache.WritebackClean_hits::total 1448 |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 8 |
| system.cpu.l2cache.ReadExReq_hits::total 8 |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 |
| system.cpu.l2cache.ReadCleanReq_hits::total 1322 |
| system.cpu.l2cache.ReadSharedReq_hits::cpu.data 57 |
| system.cpu.l2cache.ReadSharedReq_hits::total 57 |
| system.cpu.l2cache.demand_hits::cpu.inst 1322 |
| system.cpu.l2cache.demand_hits::cpu.data 65 |
| system.cpu.l2cache.demand_hits::total 1387 |
| system.cpu.l2cache.overall_hits::cpu.inst 1322 |
| system.cpu.l2cache.overall_hits::cpu.data 65 |
| system.cpu.l2cache.overall_hits::total 1387 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 |
| system.cpu.l2cache.ReadExReq_misses::total 1092 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1729 |
| system.cpu.l2cache.ReadCleanReq_misses::total 1729 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 |
| system.cpu.l2cache.ReadSharedReq_misses::total 632 |
| system.cpu.l2cache.demand_misses::cpu.inst 1729 |
| system.cpu.l2cache.demand_misses::cpu.data 1724 |
| system.cpu.l2cache.demand_misses::total 3453 |
| system.cpu.l2cache.overall_misses::cpu.inst 1729 |
| system.cpu.l2cache.overall_misses::cpu.data 1724 |
| system.cpu.l2cache.overall_misses::total 3453 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66096500 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 66096500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104697000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 104697000 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38261500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 38261500 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 104697000 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 104358000 |
| system.cpu.l2cache.demand_miss_latency::total 209055000 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 104697000 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 104358000 |
| system.cpu.l2cache.overall_miss_latency::total 209055000 |
| system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 |
| system.cpu.l2cache.WritebackDirty_accesses::total 16 |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 |
| system.cpu.l2cache.WritebackClean_accesses::total 1448 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 |
| system.cpu.l2cache.ReadExReq_accesses::total 1100 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 3051 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 689 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 689 |
| system.cpu.l2cache.demand_accesses::cpu.inst 3051 |
| system.cpu.l2cache.demand_accesses::cpu.data 1789 |
| system.cpu.l2cache.demand_accesses::total 4840 |
| system.cpu.l2cache.overall_accesses::cpu.inst 3051 |
| system.cpu.l2cache.overall_accesses::cpu.data 1789 |
| system.cpu.l2cache.overall_accesses::total 4840 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.566699 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.566699 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 |
| system.cpu.l2cache.demand_miss_rate::total 0.713430 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 |
| system.cpu.l2cache.overall_miss_rate::total 0.713430 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60527.930403 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60527.930403 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60553.499132 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60553.499132 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60540.348101 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60540.348101 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60553.499132 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60532.482599 |
| system.cpu.l2cache.demand_avg_miss_latency::total 60543.006082 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60553.499132 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60532.482599 |
| system.cpu.l2cache.overall_avg_miss_latency::total 60543.006082 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 |
| system.cpu.l2cache.demand_mshr_misses::total 3453 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 |
| system.cpu.l2cache.overall_mshr_misses::total 3453 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55176500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55176500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87407000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87407000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31941500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31941500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87407000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87118000 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 174525000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87407000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87118000 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 174525000 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 6386 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 3740 |
| system.cpu.toL2Bus.trans_dist::WritebackDirty 16 |
| system.cpu.toL2Bus.trans_dist::WritebackClean 1506 |
| system.cpu.toL2Bus.trans_dist::CleanEvict 24 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 1100 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 1100 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 |
| system.cpu.toL2Bus.pkt_count::total 11226 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 |
| system.cpu.toL2Bus.pkt_size::total 407168 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 4840 |
| system.cpu.toL2Bus.snoop_fanout::mean 0.033471 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% |
| system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 |
| system.cpu.toL2Bus.snoop_fanout::total 4840 |
| system.cpu.toL2Bus.reqLayer0.occupancy 4715000 |
| system.cpu.toL2Bus.reqLayer0.utilization 0.0 |
| system.cpu.toL2Bus.respLayer0.occupancy 4576500 |
| system.cpu.toL2Bus.respLayer0.utilization 0.0 |
| system.cpu.toL2Bus.respLayer1.occupancy 2683500 |
| system.cpu.toL2Bus.respLayer1.utilization 0.0 |
| system.membus.snoop_filter.tot_requests 3453 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 |
| system.membus.trans_dist::ReadResp 2361 |
| system.membus.trans_dist::ReadExReq 1092 |
| system.membus.trans_dist::ReadExResp 1092 |
| system.membus.trans_dist::ReadSharedReq 2361 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 |
| system.membus.pkt_count::total 6906 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 |
| system.membus.pkt_size::total 220992 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 3453 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 3453 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 3453 |
| system.membus.reqLayer0.occupancy 3601500 |
| system.membus.reqLayer0.utilization 0.0 |
| system.membus.respLayer1.occupancy 17265000 |
| system.membus.respLayer1.utilization 0.0 |
| |
| ---------- End Simulation Statistics ---------- |
