# -*- mode:python -*-

# Copyright (c) 2013 ARM Limited
# Copyright (c) 2014 Sven Karlsson
# Copyright (c) 2020 Barkhausen Institut
# Copyright (c) 2021 Huawei International
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2016 The University of Virginia
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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Import('*')

if env['TARGET_ISA'] == 'riscv':
    Source('decoder.cc')
    Source('faults.cc')
    Source('isa.cc')
    Source('locked_mem.cc')
    Source('process.cc')
    Source('pagetable.cc')
    Source('pagetable_walker.cc')
    Source('pma_checker.cc')
    Source('reg_abi.cc')
    Source('remote_gdb.cc')
    Source('tlb.cc')

    Source('linux/se_workload.cc')
    Source('linux/linux.cc')
    Source('linux/fs_workload.cc')

    Source('bare_metal/fs_workload.cc')

    SimObject('PMAChecker.py')
    SimObject('RiscvFsWorkload.py')
    SimObject('RiscvInterrupts.py')
    SimObject('RiscvISA.py')
    SimObject('RiscvMMU.py')
    SimObject('RiscvSeWorkload.py')
    SimObject('RiscvTLB.py')

    DebugFlag('RiscvMisc')
    DebugFlag('TLBVerbose')
    DebugFlag('PageTableWalker', \
              "Page table walker state machine debugging")

    # Add in files generated by the ISA description.
    ISADesc('isa/main.isa')

    GdbXml('riscv.xml', 'gdb_xml_riscv_target')
    GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
    GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
    GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')