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/*
* Copyright (c) 2013, 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
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* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
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*
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* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "dev/arm/smmu_v3_ports.hh"
#include "base/logging.hh"
#include "dev/arm/smmu_v3.hh"
#include "dev/arm/smmu_v3_deviceifc.hh"
SMMURequestPort::SMMURequestPort(const std::string &_name, SMMUv3 &_smmu) :
RequestPort(_name, &_smmu),
smmu(_smmu)
{}
bool
SMMURequestPort::recvTimingResp(PacketPtr pkt)
{
return smmu.recvTimingResp(pkt);
}
void
SMMURequestPort::recvReqRetry()
{
return smmu.recvReqRetry();
}
SMMUTableWalkPort::SMMUTableWalkPort(const std::string &_name,
SMMUv3 &_smmu) :
RequestPort(_name, &_smmu),
smmu(_smmu)
{}
bool
SMMUTableWalkPort::recvTimingResp(PacketPtr pkt)
{
return smmu.tableWalkRecvTimingResp(pkt);
}
void
SMMUTableWalkPort::recvReqRetry()
{
return smmu.tableWalkRecvReqRetry();
}
SMMUDevicePort::SMMUDevicePort(const std::string &_name,
SMMUv3DeviceInterface &_ifc,
PortID _id)
:
QueuedResponsePort(_name, &_ifc, respQueue, _id),
ifc(_ifc),
respQueue(_ifc, *this)
{}
void
SMMUDevicePort::recvFunctional(PacketPtr pkt)
{
if (!respQueue.trySatisfyFunctional(pkt))
recvAtomic(pkt);
}
Tick
SMMUDevicePort::recvAtomic(PacketPtr pkt)
{
return ifc.recvAtomic(pkt);
}
bool
SMMUDevicePort::recvTimingReq(PacketPtr pkt)
{
return ifc.recvTimingReq(pkt);
}
SMMUControlPort::SMMUControlPort(const std::string &_name,
SMMUv3 &_smmu, AddrRange _addrRange)
:
SimpleTimingPort(_name, &_smmu),
smmu(_smmu),
addrRange(_addrRange)
{}
Tick
SMMUControlPort::recvAtomic(PacketPtr pkt)
{
Addr addr = pkt->getAddr();
unsigned size = pkt->getSize();
if (!addrRange.contains(addr) || !addrRange.contains(addr+size))
panic("SMMU: invalid address on control port %x, packet size %d",
addr, size);
// @todo: We need to pay for this and not just zero it out
pkt->headerDelay = pkt->payloadDelay = 0;
return pkt->isRead() ? smmu.readControl(pkt) : smmu.writeControl(pkt);
}
AddrRangeList
SMMUControlPort::getAddrRanges() const
{
AddrRangeList list;
list.push_back(addrRange);
return list;
}
SMMUATSMemoryPort::SMMUATSMemoryPort(const std::string &_name,
SMMUv3DeviceInterface &_ifc) :
QueuedRequestPort(_name, &_ifc, reqQueue, snoopRespQueue),
ifc(_ifc),
reqQueue(_ifc, *this),
snoopRespQueue(_ifc, *this)
{}
bool
SMMUATSMemoryPort::recvTimingResp(PacketPtr pkt)
{
return ifc.atsRecvTimingResp(pkt);
}
SMMUATSDevicePort::SMMUATSDevicePort(const std::string &_name,
SMMUv3DeviceInterface &_ifc) :
QueuedResponsePort(_name, &_ifc, respQueue),
ifc(_ifc),
respQueue(_ifc, *this)
{}
void
SMMUATSDevicePort::recvFunctional(PacketPtr pkt)
{
panic("Functional access on ATS port!");
}
Tick
SMMUATSDevicePort::recvAtomic(PacketPtr pkt)
{
return ifc.atsRecvAtomic(pkt);
}
bool
SMMUATSDevicePort::recvTimingReq(PacketPtr pkt)
{
return ifc.atsRecvTimingReq(pkt);
}