commit | 2194aea0530d8af00c6ea005eeaadcc1e9071e50 | [log] [tgz] |
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author | Cui Jin <cuijinbird@gmail.com> | Tue Dec 21 23:15:03 2021 +0800 |
committer | Jin Cui <cuijinbird@gmail.com> | Wed Dec 22 23:51:50 2021 +0000 |
tree | 53c45e11ba848bc587e65f636ae18c98ff502486 | |
parent | 791092663183bcf01468ca84b6d3c177f0cf7fc7 [diff] |
arch-riscv: rvc instruction is mistaken as branch Fetch in O3CPU mistakes the normal non-branching compressed instructions, and regards it as a branch. This issue interrupts the consecutive instruction stream, thus affecting performance of cpu front-end. This fix sets the compressed for PCState during decoding. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1137 Change-Id: I7607d563bba8a08869e104877fc3c11c94cbe904 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54644 Reviewed-by: Jin Cui <cuijinbird@gmail.com> Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>