| commit | 3a0c3aecafaeabc52ba63785552ba3b6baa798e6 | [log] [tgz] |
|---|---|---|
| author | Peter <petery.hin@huawei.com> | Fri Jan 29 17:48:20 2021 +0800 |
| committer | Peter Yuen <petery.hin@huawei.com> | Tue Feb 23 03:43:47 2021 +0000 |
| tree | 0f960735bf97cf8390d6721a28c4108d8e7d6192 | |
| parent | d32c140bde4b1c0cc816f0922f2e1ef7e57717f5 [diff] |
arch-riscv: Fixing interrupt handling order and effect of mideleg This patch fixes the issues listed in: https://gem5.atlassian.net/browse/GEM5-887 https://gem5.atlassian.net/browse/GEM5-889 The code change has been verified by booting FS linux. Software, timer and external interrupts work as expected. Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40076 Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>