commit 3a1eadc04d88522a4d57ad69e84fd63b3112127c
author Tiago Mück <tiago.muck@arm.com> Thu Oct 08 11:00:13 2020 -0500
committer Tiago Mück <tiago.muck@arm.com> Mon Mar 01 22:19:13 2021 +0000
tree 4a2c1b40651d33309ab950f353f641eed0223dc4
parent 5b9517f1968ed85363d6cee2c2b29f4bd9647c13

configs: Ruby fixes for SimpleMemory

Change-Id: Idc21c8c616ef953d161685ec459765ef21ac9bc3
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41817
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs/ruby/Ruby.py

diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 4779005..2bed341 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2017-2018 ARM Limited
+# Copyright (c) 2012, 2017-2018, 2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -131,13 +131,16 @@
             dram_intf = MemConfig.create_mem_intf(mem_type, r, index,
                 options.num_dirs, int(math.log(options.num_dirs, 2)),
                 intlv_size, options.xor_low_bit)
-            mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)
+            if issubclass(mem_type, DRAMInterface):
+                mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)
+            else:
+                mem_ctrl = dram_intf
 
             if options.access_backing_store:
                 dram_intf.kvm_map=False
 
             mem_ctrls.append(mem_ctrl)
-            dir_ranges.append(mem_ctrl.dram.range)
+            dir_ranges.append(dram_intf.range)
 
             if crossbar != None:
                 mem_ctrl.port = crossbar.master