commit 3b8125d28e1313df3aebf9691bfd6b4256444367
author Hoa Nguyen <hoanguyen@ucdavis.edu> Thu Nov 03 17:30:16 2022 -0700
committer Hoa Nguyen <hoanguyen@ucdavis.edu> Fri Nov 04 21:02:29 2022 +0000
tree 7c82711c9c2de5ef57b83dd6a3fdfbe5b252e04a
parent 26c27b1bf8c7aac351f90db9f0dccc775b6d8caa

arch-riscv: Add VS field to the STATUS CSR

Per RISC-V ISA Manual, vol II, section 3.1.6, page 20, the VS field
is located at bits 10..9 of mstatus. Per section 4.1.1, page 63,
the VS field is located at the same bits of sstatus.

Change-Id: Ifda44441c551a23ed892fb8ac7ef31fa98f0b6db
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65274
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/regs/misc.hh

diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index cb8c907..5f07447 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -562,6 +562,7 @@
     Bitfield<16, 15> xs;
     Bitfield<14, 13> fs;
     Bitfield<12, 11> mpp;
+    Bitfield<10, 9> vs;
     Bitfield<8> spp;
     Bitfield<7> mpie;
     Bitfield<5> spie;
@@ -612,6 +613,7 @@
 const RegVal STATUS_XS_MASK = 3ULL << 15;
 const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
 const RegVal STATUS_MPP_MASK = 3ULL << 11;
+const RegVal STATUS_VS_MASK = 3ULL << 9;
 const RegVal STATUS_SPP_MASK = 1ULL << 8;
 const RegVal STATUS_MPIE_MASK = 1ULL << 7;
 const RegVal STATUS_SPIE_MASK = 1ULL << 5;
@@ -624,21 +626,21 @@
                             STATUS_TW_MASK | STATUS_TVM_MASK |
                             STATUS_MXR_MASK | STATUS_SUM_MASK |
                             STATUS_MPRV_MASK | STATUS_XS_MASK |
-                            STATUS_FS_MASK | STATUS_MPP_MASK |
-                            STATUS_SPP_MASK | STATUS_MPIE_MASK |
-                            STATUS_SPIE_MASK | STATUS_UPIE_MASK |
-                            STATUS_MIE_MASK | STATUS_SIE_MASK |
-                            STATUS_UIE_MASK;
+                            STATUS_FS_MASK | STATUS_VS_MASK |
+                            STATUS_MPP_MASK | STATUS_SPP_MASK |
+                            STATUS_MPIE_MASK | STATUS_SPIE_MASK |
+                            STATUS_UPIE_MASK | STATUS_MIE_MASK |
+                            STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
                             STATUS_MXR_MASK | STATUS_SUM_MASK |
                             STATUS_XS_MASK | STATUS_FS_MASK |
-                            STATUS_SPP_MASK | STATUS_SPIE_MASK |
-                            STATUS_UPIE_MASK | STATUS_SIE_MASK |
-                            STATUS_UIE_MASK;
+                            STATUS_VS_MASK | STATUS_SPP_MASK |
+                            STATUS_SPIE_MASK | STATUS_UPIE_MASK |
+                            STATUS_SIE_MASK | STATUS_UIE_MASK;
 const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
                             STATUS_SUM_MASK | STATUS_XS_MASK |
-                            STATUS_FS_MASK | STATUS_UPIE_MASK |
-                            STATUS_UIE_MASK;
+                            STATUS_FS_MASK | STATUS_VS_MASK |
+                            STATUS_UPIE_MASK | STATUS_UIE_MASK;
 
 const RegVal MEI_MASK = 1ULL << 11;
 const RegVal SEI_MASK = 1ULL << 9;