| # Copyright (c) 2008 The Hewlett-Packard Development Company |
| # Copyright (c) 2018 Metempsy Technology Consulting |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
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| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
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| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| |
| from m5.params import * |
| from m5.SimObject import SimObject |
| |
| class BaseTLB(SimObject): |
| type = 'BaseTLB' |
| abstract = True |
| cxx_header = "arch/generic/tlb.hh" |
| cxx_class = 'gem5::BaseTLB' |
| |
| # Ports to connect with other TLB levels |
| cpu_side_ports = VectorResponsePort("Ports closer to the CPU side") |
| slave = DeprecatedParam(cpu_side_ports, |
| '`slave` is now called `cpu_side_ports`') |
| mem_side_port = RequestPort("Port closer to memory side") |
| master = DeprecatedParam(mem_side_port, |
| '`master` is now called `mem_side_port`') |