commit 404b86813e73762cdce537c440abb16f6ab1bb97
author Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Jul 23 16:34:26 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Jul 25 12:49:12 2019 +0000
tree 43724a75480ce9645bd00e63ca2ad4243541bcfc
parent e71e2d6a35233250ad05b358c27cad5a05609d55

dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache

Otherwise a hit after a table walk will result in a 0 value being
read from the ConfigCache.

Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/smmu_v3_caches.hh

diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh
index ce5bb45..060f60e 100644
--- a/src/dev/arm/smmu_v3_caches.hh
+++ b/src/dev/arm/smmu_v3_caches.hh
@@ -252,6 +252,8 @@
         uint16_t vmid;
         uint8_t stage1_tg;
         uint8_t stage2_tg;
+        uint8_t t0sz;
+        uint8_t s2t0sz;
     };
 
     ConfigCache(unsigned numEntries, unsigned _associativity,

src/dev/arm/smmu_v3_transl.cc

diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index 84ca5a7..c1d998e 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -532,6 +532,9 @@
     tc.stage1TranslGranule = e->stage1_tg;
     tc.stage2TranslGranule = e->stage2_tg;
 
+    tc.t0sz = e->t0sz;
+    tc.s2t0sz = e->s2t0sz;
+
     return true;
 }
 
@@ -555,6 +558,8 @@
     e.vmid = tc.vmid;
     e.stage1_tg = tc.stage1TranslGranule;
     e.stage2_tg = tc.stage2TranslGranule;
+    e.t0sz = tc.t0sz;
+    e.s2t0sz = tc.s2t0sz;
 
     doSemaphoreDown(yield, smmu.configSem);