diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh
index ce5bb45..060f60e 100644
--- a/src/dev/arm/smmu_v3_caches.hh
+++ b/src/dev/arm/smmu_v3_caches.hh
@@ -252,6 +252,8 @@
         uint16_t vmid;
         uint8_t stage1_tg;
         uint8_t stage2_tg;
+        uint8_t t0sz;
+        uint8_t s2t0sz;
     };
 
     ConfigCache(unsigned numEntries, unsigned _associativity,
diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index 84ca5a7..c1d998e 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -532,6 +532,9 @@
     tc.stage1TranslGranule = e->stage1_tg;
     tc.stage2TranslGranule = e->stage2_tg;
 
+    tc.t0sz = e->t0sz;
+    tc.s2t0sz = e->s2t0sz;
+
     return true;
 }
 
@@ -555,6 +558,8 @@
     e.vmid = tc.vmid;
     e.stage1_tg = tc.stage1TranslGranule;
     e.stage2_tg = tc.stage2TranslGranule;
+    e.t0sz = tc.t0sz;
+    e.s2t0sz = tc.s2t0sz;
 
     doSemaphoreDown(yield, smmu.configSem);