| commit | 411e986a91473c329279bf8c50d7ae4df3048e0a | [log] [tgz] |
|---|---|---|
| author | yiwkd2 <yiwkd2@gmail.com> | Wed Aug 24 03:32:45 2022 -0400 |
| committer | Youngin Kim <yiwkd2@gmail.com> | Thu Sep 01 03:22:56 2022 +0000 |
| tree | 9c159e1d1e44abcae5603c418bbae948a0c93855 | |
| parent | 9f206c2bfcf9bbcc6053a62b8f96eaa2c19b7533 [diff] |
stdlib: Add PrivateL1SharedL2CacheHierarchy This is implemented based on PrivateL1PrivateL2CacheHierarchy Following modifications are made. * The associativities of caches are parameterized * Only single L2bus and L2cache exist * Connections of L2cache (i.e., l2bus - l2cache, membus - l2cache) are done out of for loop which is repeated num_cpus times. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1274 Change-Id: I1307954ffff4fab2bf5f61e225881b03a352a1e1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62655 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>