| commit | 41ee8ec7d8578b87b4f9b50440f82c57a544cc62 | [log] [tgz] |
|---|---|---|
| author | Austin Harris <mail@austin-harris.com> | Mon Jan 10 18:20:52 2022 -0600 |
| committer | Austin Harris <mail@austin-harris.com> | Mon Jan 17 15:15:24 2022 +0000 |
| tree | 50d70942fd2370eea30d5a60ebf992a17d64bc7d | |
| parent | ef4381aecc2b70b63b0bda5e5fa5ca10c57d4e67 [diff] |
mem: implement x86 locked accesses in timing-mode classic cache Add LockedRMW(Read|Write)(Req|Resp) commands. In timing mode, use a combination of clearing permission bits and leaving an MSHR in place to prevent accesses & snoops from touching a locked block between the read and write parts of an locked RMW sequence. Based on an old patch by Steve Reinhardt: http://reviews.gem5.org/r/2691/index.html Jira Issue: https://gem5.atlassian.net/browse/GEM5-1105 Change-Id: Ieadda4deb17667ca4a6282f87f6da2af3b011f66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52303 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>