| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.225185 # Number of seconds simulated |
| sim_ticks 225184887000 # Number of ticks simulated |
| final_tick 225184887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 292846 # Simulator instruction rate (inst/s) |
| host_op_rate 351594 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 241521552 # Simulator tick rate (ticks/s) |
| host_mem_usage 280036 # Number of bytes of host memory used |
| host_seconds 932.36 # Real time elapsed on the host |
| sim_insts 273037855 # Number of instructions simulated |
| sim_ops 327812212 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 485504 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory |
| system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 972854 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 1183170 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 2156024 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 972854 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 972854 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 972854 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 1183170 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 2156024 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.readReqs 7586 # Number of read requests accepted |
| system.physmem.writeReqs 0 # Number of write requests accepted |
| system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue |
| system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM |
| system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue |
| system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side |
| system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side |
| system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue |
| system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| system.physmem.perBankRdBursts::0 630 # Per bank write bursts |
| system.physmem.perBankRdBursts::1 846 # Per bank write bursts |
| system.physmem.perBankRdBursts::2 628 # Per bank write bursts |
| system.physmem.perBankRdBursts::3 541 # Per bank write bursts |
| system.physmem.perBankRdBursts::4 466 # Per bank write bursts |
| system.physmem.perBankRdBursts::5 349 # Per bank write bursts |
| system.physmem.perBankRdBursts::6 171 # Per bank write bursts |
| system.physmem.perBankRdBursts::7 228 # Per bank write bursts |
| system.physmem.perBankRdBursts::8 208 # Per bank write bursts |
| system.physmem.perBankRdBursts::9 309 # Per bank write bursts |
| system.physmem.perBankRdBursts::10 343 # Per bank write bursts |
| system.physmem.perBankRdBursts::11 428 # Per bank write bursts |
| system.physmem.perBankRdBursts::12 553 # Per bank write bursts |
| system.physmem.perBankRdBursts::13 705 # Per bank write bursts |
| system.physmem.perBankRdBursts::14 639 # Per bank write bursts |
| system.physmem.perBankRdBursts::15 542 # Per bank write bursts |
| system.physmem.perBankWrBursts::0 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::1 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::2 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::3 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::4 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::5 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::6 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::7 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::8 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::9 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::10 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::11 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::12 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::13 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::14 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::15 0 # Per bank write bursts |
| system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| system.physmem.totGap 225184633000 # Total gap between requests |
| system.physmem.readPktSize::0 0 # Read request sizes (log2) |
| system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| system.physmem.readPktSize::2 0 # Read request sizes (log2) |
| system.physmem.readPktSize::3 0 # Read request sizes (log2) |
| system.physmem.readPktSize::4 0 # Read request sizes (log2) |
| system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| system.physmem.readPktSize::6 7586 # Read request sizes (log2) |
| system.physmem.writePktSize::0 0 # Write request sizes (log2) |
| system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| system.physmem.writePktSize::2 0 # Write request sizes (log2) |
| system.physmem.writePktSize::3 0 # Write request sizes (log2) |
| system.physmem.writePktSize::4 0 # Write request sizes (log2) |
| system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| system.physmem.rdQLenPdf::0 6690 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| system.physmem.bytesPerActivate::samples 1509 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::mean 321.017893 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::gmean 191.649066 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::stdev 328.624854 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::0-127 538 35.65% 35.65% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::128-255 351 23.26% 58.91% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::256-383 166 11.00% 69.91% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::384-511 79 5.24% 75.15% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::512-639 78 5.17% 80.32% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::640-767 56 3.71% 84.03% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::768-895 32 2.12% 86.15% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::896-1023 36 2.39% 88.54% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::1024-1151 173 11.46% 100.00% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::total 1509 # Bytes accessed per row activation |
| system.physmem.totQLat 232077250 # Total ticks spent queuing |
| system.physmem.totMemAccLat 374314750 # Total ticks spent from burst creation until serviced by the DRAM |
| system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers |
| system.physmem.avgQLat 30592.84 # Average queueing delay per DRAM burst |
| system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| system.physmem.avgMemAccLat 49342.84 # Average memory access latency per DRAM burst |
| system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s |
| system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s |
| system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s |
| system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| system.physmem.busUtil 0.02 # Data bus utilization in percentage |
| system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads |
| system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| system.physmem.readRowHits 6074 # Number of row buffer hits during reads |
| system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads |
| system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| system.physmem.avgGap 29684238.47 # Average gap between requests |
| system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined |
| system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) |
| system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) |
| system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) |
| system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_0.actBackEnergy 100520070 # Energy for active background per rank (pJ) |
| system.physmem_0.preBackEnergy 15505920 # Energy for precharge background per rank (pJ) |
| system.physmem_0.actPowerDownEnergy 721291110 # Energy for active power-down per rank (pJ) |
| system.physmem_0.prePowerDownEnergy 385301760 # Energy for precharge power-down per rank (pJ) |
| system.physmem_0.selfRefreshEnergy 53419321200 # Energy for self refresh per rank (pJ) |
| system.physmem_0.totalEnergy 54961303020 # Total energy per rank (pJ) |
| system.physmem_0.averagePower 244.071899 # Core power per rank (mW) |
| system.physmem_0.totalIdleTime 224923904000 # Total Idle time Per DRAM Rank |
| system.physmem_0.memoryStateTime::IDLE 29388000 # Time in different power states |
| system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states |
| system.physmem_0.memoryStateTime::SREF 222338897000 # Time in different power states |
| system.physmem_0.memoryStateTime::PRE_PDN 1003385750 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT 110367750 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT_PDN 1581838500 # Time in different power states |
| system.physmem_1.actEnergy 6069000 # Energy for activate commands per rank (pJ) |
| system.physmem_1.preEnergy 3221955 # Energy for precharge commands per rank (pJ) |
| system.physmem_1.readEnergy 26610780 # Energy for read commands per rank (pJ) |
| system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_1.actBackEnergy 121194540 # Energy for active background per rank (pJ) |
| system.physmem_1.preBackEnergy 22344960 # Energy for precharge background per rank (pJ) |
| system.physmem_1.actPowerDownEnergy 914224140 # Energy for active power-down per rank (pJ) |
| system.physmem_1.prePowerDownEnergy 605228160 # Energy for precharge power-down per rank (pJ) |
| system.physmem_1.selfRefreshEnergy 53190600045 # Energy for self refresh per rank (pJ) |
| system.physmem_1.totalEnergy 55284153510 # Total energy per rank (pJ) |
| system.physmem_1.averagePower 245.505612 # Core power per rank (mW) |
| system.physmem_1.totalIdleTime 224860041750 # Total Idle time Per DRAM Rank |
| system.physmem_1.memoryStateTime::IDLE 42127000 # Time in different power states |
| system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states |
| system.physmem_1.memoryStateTime::SREF 221279795000 # Time in different power states |
| system.physmem_1.memoryStateTime::PRE_PDN 1576124250 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT 114092500 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT_PDN 2004910250 # Time in different power states |
| system.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.branchPred.lookups 32421416 # Number of BP lookups |
| system.cpu.branchPred.condPredicted 16919401 # Number of conditional branches predicted |
| system.cpu.branchPred.condIncorrect 734831 # Number of conditional branches incorrect |
| system.cpu.branchPred.BTBLookups 17534346 # Number of BTB lookups |
| system.cpu.branchPred.BTBHits 12860140 # Number of BTB hits |
| system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu.branchPred.BTBHitPct 73.342570 # BTB Hit Percentage |
| system.cpu.branchPred.usedRAS 6521085 # Number of times the RAS was used to get a target. |
| system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. |
| system.cpu.branchPred.indirectLookups 2302887 # Number of indirect predictor lookups. |
| system.cpu.branchPred.indirectHits 2263691 # Number of indirect target hits. |
| system.cpu.branchPred.indirectMisses 39196 # Number of indirect misses. |
| system.cpu.branchPredindirectMispredicted 128438 # Number of mispredicted indirect branches. |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.dtb.walker.walks 0 # Table walker walks requested |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.inst_hits 0 # ITB inst hits |
| system.cpu.dtb.inst_misses 0 # ITB inst misses |
| system.cpu.dtb.read_hits 0 # DTB read hits |
| system.cpu.dtb.read_misses 0 # DTB read misses |
| system.cpu.dtb.write_hits 0 # DTB write hits |
| system.cpu.dtb.write_misses 0 # DTB write misses |
| system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dtb.read_accesses 0 # DTB read accesses |
| system.cpu.dtb.write_accesses 0 # DTB write accesses |
| system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dtb.hits 0 # DTB hits |
| system.cpu.dtb.misses 0 # DTB misses |
| system.cpu.dtb.accesses 0 # DTB accesses |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.itb.walker.walks 0 # Table walker walks requested |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.inst_hits 0 # ITB inst hits |
| system.cpu.itb.inst_misses 0 # ITB inst misses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.inst_accesses 0 # ITB inst accesses |
| system.cpu.itb.hits 0 # DTB hits |
| system.cpu.itb.misses 0 # DTB misses |
| system.cpu.itb.accesses 0 # DTB accesses |
| system.cpu.workload.numSyscalls 191 # Number of system calls |
| system.cpu.pwrStateResidencyTicks::ON 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.numCycles 450369774 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.committedInsts 273037855 # Number of instructions committed |
| system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed |
| system.cpu.discardedOps 2044614 # Number of ops (including micro ops) which were discarded before commit |
| system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| system.cpu.cpi 1.649477 # CPI: cycles per instruction |
| system.cpu.ipc 0.606253 # IPC: instructions per cycle |
| system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction |
| system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction |
| system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction |
| system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::total 327812212 # Class of committed instruction |
| system.cpu.tickCycles 434912818 # Number of cycles that the object actually ticked |
| system.cpu.idleCycles 15456956 # Total number of cycles that the object has spent stopped |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.tags.replacements 1355 # number of replacements |
| system.cpu.dcache.tags.tagsinuse 3085.765100 # Cycle average of tags in use |
| system.cpu.dcache.tags.total_refs 168647477 # Total number of references to valid blocks. |
| system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. |
| system.cpu.dcache.tags.avg_refs 37377.543661 # Average number of references to valid blocks. |
| system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.tags.occ_blocks::cpu.data 3085.765100 # Average occupied blocks per requestor |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id |
| system.cpu.dcache.tags.tag_accesses 337313356 # Number of tag accesses |
| system.cpu.dcache.tags.data_accesses 337313356 # Number of data accesses |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.ReadReq_hits::cpu.data 86514704 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 86514704 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits |
| system.cpu.dcache.SoftPFReq_hits::cpu.data 63536 # number of SoftPFReq hits |
| system.cpu.dcache.SoftPFReq_hits::total 63536 # number of SoftPFReq hits |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits |
| system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits |
| system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits |
| system.cpu.dcache.demand_hits::cpu.data 168562151 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 168562151 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 168625687 # number of overall hits |
| system.cpu.dcache.overall_hits::total 168625687 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses |
| system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses |
| system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses |
| system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses |
| system.cpu.dcache.overall_misses::total 6945 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 177071500 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 177071500 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 487051000 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 487051000 # number of WriteReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 664122500 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 664122500 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 664122500 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 664122500 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 86516414 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 86516414 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::cpu.data 63541 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::total 63541 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 168569091 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 168569091 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 168632632 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 168632632 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103550.584795 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 103550.584795 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93126.386233 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 93126.386233 # average WriteReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 95694.884726 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 95694.884726 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 95625.989921 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 95625.989921 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks |
| system.cpu.dcache.writebacks::total 1010 # number of writebacks |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits |
| system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits |
| system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits |
| system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171838500 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 171838500 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285292000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 285292000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457130500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 457130500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 457389500 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 457389500 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104843.502135 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104843.502135 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99404.878049 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99404.878049 # average WriteReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101381.791972 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 101381.791972 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101371.786348 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 101371.786348 # average overall mshr miss latency |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.tags.replacements 38251 # number of replacements |
| system.cpu.icache.tags.tagsinuse 1924.799688 # Cycle average of tags in use |
| system.cpu.icache.tags.total_refs 69805458 # Total number of references to valid blocks. |
| system.cpu.icache.tags.sampled_refs 40188 # Sample count of references to valid blocks. |
| system.cpu.icache.tags.avg_refs 1736.972678 # Average number of references to valid blocks. |
| system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.tags.occ_blocks::cpu.inst 1924.799688 # Average occupied blocks per requestor |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id |
| system.cpu.icache.tags.tag_accesses 139731482 # Number of tag accesses |
| system.cpu.icache.tags.data_accesses 139731482 # Number of data accesses |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.ReadReq_hits::cpu.inst 69805458 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 69805458 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 69805458 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 69805458 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 69805458 # number of overall hits |
| system.cpu.icache.overall_hits::total 69805458 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 40189 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 40189 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 40189 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 40189 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 40189 # number of overall misses |
| system.cpu.icache.overall_misses::total 40189 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 818936000 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 818936000 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 818936000 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 818936000 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 818936000 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 818936000 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 69845647 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 69845647 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 69845647 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 69845647 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 69845647 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 69845647 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000575 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.000575 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.000575 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.000575 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.000575 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.000575 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20377.118117 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 20377.118117 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 20377.118117 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 20377.118117 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.writebacks::writebacks 38251 # number of writebacks |
| system.cpu.icache.writebacks::total 38251 # number of writebacks |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40189 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 40189 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 40189 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 40189 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 40189 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 40189 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 778748000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 778748000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 778748000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 778748000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 778748000 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 778748000 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000575 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.000575 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.000575 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19377.142999 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19377.142999 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.tags.replacements 0 # number of replacements |
| system.cpu.l2cache.tags.tagsinuse 6596.199570 # Cycle average of tags in use |
| system.cpu.l2cache.tags.total_refs 61643 # Total number of references to valid blocks. |
| system.cpu.l2cache.tags.sampled_refs 7586 # Sample count of references to valid blocks. |
| system.cpu.l2cache.tags.avg_refs 8.125890 # Average number of references to valid blocks. |
| system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.827893 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.371677 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096674 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::total 0.201300 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 7586 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::3 788 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231506 # Percentage of cache occupancy per task id |
| system.cpu.l2cache.tags.tag_accesses 561762 # Number of tag accesses |
| system.cpu.l2cache.tags.data_accesses 561762 # Number of data accesses |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackClean_hits::writebacks 23333 # number of WritebackClean hits |
| system.cpu.l2cache.WritebackClean_hits::total 23333 # number of WritebackClean hits |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits |
| system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36764 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::total 36764 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::cpu.data 292 # number of ReadSharedReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::total 292 # number of ReadSharedReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 36764 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::cpu.data 308 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 37072 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 36764 # number of overall hits |
| system.cpu.l2cache.overall_hits::cpu.data 308 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 37072 # number of overall hits |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 7629 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 7629 # number of overall misses |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 280789500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 280789500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317508500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 317508500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166371500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 166371500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 317508500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 447161000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 764669500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 317508500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 447161000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 764669500 # number of overall miss cycles |
| system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 23333 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::total 23333 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40189 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::total 40189 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 40189 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 44701 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 40189 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 44701 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085222 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085222 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085222 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.170667 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085222 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.170667 # miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98384.548003 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98384.548003 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92703.211679 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92703.211679 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123238.148148 # average ReadSharedReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123238.148148 # average ReadSharedReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 100231.943898 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 100231.943898 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 41 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::total 41 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252249500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252249500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283130000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283130000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150320500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150320500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283130000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 402570000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 685700000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283130000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 402570000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 685700000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085173 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.169705 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.169705 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88384.548003 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88384.548003 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82713.993573 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82713.993573 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114836.134454 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114836.134454 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency |
| system.cpu.toL2Bus.snoop_filter.tot_requests 84307 # Total number of requests made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 39708 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.cpu.toL2Bus.trans_dist::ReadResp 41830 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackClean 38251 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 40189 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118628 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count::total 129007 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5020096 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size::total 5373504 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.cpu.toL2Bus.snoop_fanout::samples 44701 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::mean 0.338628 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.473248 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::0 29564 66.14% 66.14% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::1 15137 33.86% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::total 44701 # Request fanout histogram |
| system.cpu.toL2Bus.reqLayer0.occupancy 81414500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer0.occupancy 60282998 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| system.membus.snoop_filter.tot_requests 7586 # Total number of requests made to the snoop filter. |
| system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states |
| system.membus.trans_dist::ReadResp 4732 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 2854 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 2854 # Transaction distribution |
| system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 0 # Total snoops (count) |
| system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.membus.snoop_fanout::samples 7586 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::total 7586 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 9076000 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 40293000 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
| |
| ---------- End Simulation Statistics ---------- |
