| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.517298 |
| sim_ticks 517297855500 |
| final_tick 517297855500 |
| sim_freq 1000000000000 |
| host_inst_rate 473413 |
| host_op_rate 568350 |
| host_tick_rate 897909978 |
| host_mem_usage 288888 |
| host_seconds 576.11 |
| sim_insts 272739286 |
| sim_ops 327433744 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.physmem.bytes_read::cpu.inst 166912 |
| system.physmem.bytes_read::cpu.data 270336 |
| system.physmem.bytes_read::total 437248 |
| system.physmem.bytes_inst_read::cpu.inst 166912 |
| system.physmem.bytes_inst_read::total 166912 |
| system.physmem.num_reads::cpu.inst 2608 |
| system.physmem.num_reads::cpu.data 4224 |
| system.physmem.num_reads::total 6832 |
| system.physmem.bw_read::cpu.inst 322661 |
| system.physmem.bw_read::cpu.data 522593 |
| system.physmem.bw_read::total 845254 |
| system.physmem.bw_inst_read::cpu.inst 322661 |
| system.physmem.bw_inst_read::total 322661 |
| system.physmem.bw_total::cpu.inst 322661 |
| system.physmem.bw_total::cpu.data 522593 |
| system.physmem.bw_total::total 845254 |
| system.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 191 |
| system.cpu.pwrStateResidencyTicks::ON 517297855500 |
| system.cpu.numCycles 1034595711 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 272739286 |
| system.cpu.committedOps 327433744 |
| system.cpu.num_int_alu_accesses 258331537 |
| system.cpu.num_fp_alu_accesses 114216705 |
| system.cpu.num_func_calls 12448615 |
| system.cpu.num_conditional_control_insts 15799349 |
| system.cpu.num_int_insts 258331537 |
| system.cpu.num_fp_insts 114216705 |
| system.cpu.num_int_register_reads 979511506 |
| system.cpu.num_int_register_writes 162499693 |
| system.cpu.num_fp_register_reads 180262959 |
| system.cpu.num_fp_register_writes 126152315 |
| system.cpu.num_cc_register_reads 1242915503 |
| system.cpu.num_cc_register_writes 76361814 |
| system.cpu.num_mem_refs 168107847 |
| system.cpu.num_load_insts 85732248 |
| system.cpu.num_store_insts 82375599 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 1034595711 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 30563503 |
| system.cpu.op_class::No_OpClass 0 0.00% 0.00% |
| system.cpu.op_class::IntAlu 104312544 31.82% 31.82% |
| system.cpu.op_class::IntMult 2145905 0.65% 32.48% |
| system.cpu.op_class::IntDiv 0 0.00% 32.48% |
| system.cpu.op_class::FloatAdd 0 0.00% 32.48% |
| system.cpu.op_class::FloatCmp 0 0.00% 32.48% |
| system.cpu.op_class::FloatCvt 0 0.00% 32.48% |
| system.cpu.op_class::FloatMult 0 0.00% 32.48% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% |
| system.cpu.op_class::FloatDiv 0 0.00% 32.48% |
| system.cpu.op_class::FloatMisc 0 0.00% 32.48% |
| system.cpu.op_class::FloatSqrt 0 0.00% 32.48% |
| system.cpu.op_class::SimdAdd 0 0.00% 32.48% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% |
| system.cpu.op_class::SimdAlu 0 0.00% 32.48% |
| system.cpu.op_class::SimdCmp 0 0.00% 32.48% |
| system.cpu.op_class::SimdCvt 0 0.00% 32.48% |
| system.cpu.op_class::SimdMisc 0 0.00% 32.48% |
| system.cpu.op_class::SimdMult 0 0.00% 32.48% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% |
| system.cpu.op_class::SimdShift 0 0.00% 32.48% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% |
| system.cpu.op_class::SimdSqrt 0 0.00% 32.48% |
| system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% |
| system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% |
| system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% |
| system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% |
| system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% |
| system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% |
| system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% |
| system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% |
| system.cpu.op_class::MemRead 44185174 13.48% 62.20% |
| system.cpu.op_class::MemWrite 55008381 16.78% 78.98% |
| system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% |
| system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 327812214 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.dcache.tags.replacements 1332 |
| system.cpu.dcache.tags.tagsinuse 3078.320204 |
| system.cpu.dcache.tags.total_refs 168359617 |
| system.cpu.dcache.tags.sampled_refs 4478 |
| system.cpu.dcache.tags.avg_refs 37597.056052 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 |
| system.cpu.dcache.tags.occ_percent::total 0.751543 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 |
| system.cpu.dcache.tags.tag_accesses 336732670 |
| system.cpu.dcache.tags.data_accesses 336732670 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.dcache.ReadReq_hits::cpu.data 86233963 |
| system.cpu.dcache.ReadReq_hits::total 86233963 |
| system.cpu.dcache.WriteReq_hits::cpu.data 82049805 |
| system.cpu.dcache.WriteReq_hits::total 82049805 |
| system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 |
| system.cpu.dcache.SoftPFReq_hits::total 54059 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 |
| system.cpu.dcache.LoadLockedReq_hits::total 10895 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 |
| system.cpu.dcache.StoreCondReq_hits::total 10895 |
| system.cpu.dcache.demand_hits::cpu.data 168283768 |
| system.cpu.dcache.demand_hits::total 168283768 |
| system.cpu.dcache.overall_hits::cpu.data 168337827 |
| system.cpu.dcache.overall_hits::total 168337827 |
| system.cpu.dcache.ReadReq_misses::cpu.data 1604 |
| system.cpu.dcache.ReadReq_misses::total 1604 |
| system.cpu.dcache.WriteReq_misses::cpu.data 2872 |
| system.cpu.dcache.WriteReq_misses::total 2872 |
| system.cpu.dcache.SoftPFReq_misses::cpu.data 3 |
| system.cpu.dcache.SoftPFReq_misses::total 3 |
| system.cpu.dcache.demand_misses::cpu.data 4476 |
| system.cpu.dcache.demand_misses::total 4476 |
| system.cpu.dcache.overall_misses::cpu.data 4479 |
| system.cpu.dcache.overall_misses::total 4479 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 |
| system.cpu.dcache.ReadReq_miss_latency::total 89418000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 |
| system.cpu.dcache.WriteReq_miss_latency::total 180278500 |
| system.cpu.dcache.demand_miss_latency::cpu.data 269696500 |
| system.cpu.dcache.demand_miss_latency::total 269696500 |
| system.cpu.dcache.overall_miss_latency::cpu.data 269696500 |
| system.cpu.dcache.overall_miss_latency::total 269696500 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 |
| system.cpu.dcache.ReadReq_accesses::total 86235567 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 |
| system.cpu.dcache.WriteReq_accesses::total 82052677 |
| system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 |
| system.cpu.dcache.SoftPFReq_accesses::total 54062 |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 |
| system.cpu.dcache.LoadLockedReq_accesses::total 10895 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 |
| system.cpu.dcache.StoreCondReq_accesses::total 10895 |
| system.cpu.dcache.demand_accesses::cpu.data 168288244 |
| system.cpu.dcache.demand_accesses::total 168288244 |
| system.cpu.dcache.overall_accesses::cpu.data 168342306 |
| system.cpu.dcache.overall_accesses::total 168342306 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.000019 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.000035 |
| system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 |
| system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 |
| system.cpu.dcache.demand_miss_rate::total 0.000027 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 |
| system.cpu.dcache.overall_miss_rate::total 0.000027 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 |
| system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 |
| system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu.dcache.writebacks::writebacks 998 |
| system.cpu.dcache.writebacks::total 998 |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 |
| system.cpu.dcache.ReadReq_mshr_hits::total 1 |
| system.cpu.dcache.demand_mshr_hits::cpu.data 1 |
| system.cpu.dcache.demand_mshr_hits::total 1 |
| system.cpu.dcache.overall_mshr_hits::cpu.data 1 |
| system.cpu.dcache.overall_mshr_hits::total 1 |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 |
| system.cpu.dcache.ReadReq_mshr_misses::total 1603 |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 |
| system.cpu.dcache.WriteReq_mshr_misses::total 2872 |
| system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 |
| system.cpu.dcache.SoftPFReq_mshr_misses::total 3 |
| system.cpu.dcache.demand_mshr_misses::cpu.data 4475 |
| system.cpu.dcache.demand_mshr_misses::total 4475 |
| system.cpu.dcache.overall_mshr_misses::cpu.data 4478 |
| system.cpu.dcache.overall_mshr_misses::total 4478 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 |
| system.cpu.dcache.demand_mshr_miss_latency::total 265173500 |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 |
| system.cpu.dcache.overall_mshr_miss_latency::total 265359500 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.icache.tags.replacements 13796 |
| system.cpu.icache.tags.tagsinuse 1765.939670 |
| system.cpu.icache.tags.total_refs 348644750 |
| system.cpu.icache.tags.sampled_refs 15603 |
| system.cpu.icache.tags.avg_refs 22344.725373 |
| system.cpu.icache.tags.warmup_cycle 0 |
| system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 |
| system.cpu.icache.tags.occ_percent::total 0.862275 |
| system.cpu.icache.tags.occ_task_id_blocks::1024 1807 |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 30 |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 66 |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 26 |
| system.cpu.icache.tags.age_task_id_blocks_1024::3 161 |
| system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 |
| system.cpu.icache.tags.tag_accesses 697336309 |
| system.cpu.icache.tags.data_accesses 697336309 |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.icache.ReadReq_hits::cpu.inst 348644750 |
| system.cpu.icache.ReadReq_hits::total 348644750 |
| system.cpu.icache.demand_hits::cpu.inst 348644750 |
| system.cpu.icache.demand_hits::total 348644750 |
| system.cpu.icache.overall_hits::cpu.inst 348644750 |
| system.cpu.icache.overall_hits::total 348644750 |
| system.cpu.icache.ReadReq_misses::cpu.inst 15603 |
| system.cpu.icache.ReadReq_misses::total 15603 |
| system.cpu.icache.demand_misses::cpu.inst 15603 |
| system.cpu.icache.demand_misses::total 15603 |
| system.cpu.icache.overall_misses::cpu.inst 15603 |
| system.cpu.icache.overall_misses::total 15603 |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 |
| system.cpu.icache.ReadReq_miss_latency::total 341054000 |
| system.cpu.icache.demand_miss_latency::cpu.inst 341054000 |
| system.cpu.icache.demand_miss_latency::total 341054000 |
| system.cpu.icache.overall_miss_latency::cpu.inst 341054000 |
| system.cpu.icache.overall_miss_latency::total 341054000 |
| system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 |
| system.cpu.icache.ReadReq_accesses::total 348660353 |
| system.cpu.icache.demand_accesses::cpu.inst 348660353 |
| system.cpu.icache.demand_accesses::total 348660353 |
| system.cpu.icache.overall_accesses::cpu.inst 348660353 |
| system.cpu.icache.overall_accesses::total 348660353 |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 |
| system.cpu.icache.ReadReq_miss_rate::total 0.000045 |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 |
| system.cpu.icache.demand_miss_rate::total 0.000045 |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 |
| system.cpu.icache.overall_miss_rate::total 0.000045 |
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| system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 |
| system.cpu.icache.demand_avg_miss_latency::total 21858.232391 |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 |
| system.cpu.icache.overall_avg_miss_latency::total 21858.232391 |
| system.cpu.icache.blocked_cycles::no_mshrs 0 |
| system.cpu.icache.blocked_cycles::no_targets 0 |
| system.cpu.icache.blocked::no_mshrs 0 |
| system.cpu.icache.blocked::no_targets 0 |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.writebacks::writebacks 13796 |
| system.cpu.icache.writebacks::total 13796 |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 |
| system.cpu.icache.ReadReq_mshr_misses::total 15603 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 15603 |
| system.cpu.icache.demand_mshr_misses::total 15603 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 15603 |
| system.cpu.icache.overall_mshr_misses::total 15603 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 |
| system.cpu.icache.demand_mshr_miss_latency::total 325451000 |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 |
| system.cpu.icache.overall_mshr_miss_latency::total 325451000 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 |
| system.cpu.icache.demand_mshr_miss_rate::total 0.000045 |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 |
| system.cpu.icache.overall_mshr_miss_rate::total 0.000045 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 5901.352793 |
| system.cpu.l2cache.tags.total_refs 20712 |
| system.cpu.l2cache.tags.sampled_refs 6832 |
| system.cpu.l2cache.tags.avg_refs 3.031616 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 |
| system.cpu.l2cache.tags.occ_percent::total 0.180095 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 |
| system.cpu.l2cache.tags.tag_accesses 227184 |
| system.cpu.l2cache.tags.data_accesses 227184 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.l2cache.WritebackDirty_hits::writebacks 998 |
| system.cpu.l2cache.WritebackDirty_hits::total 998 |
| system.cpu.l2cache.WritebackClean_hits::writebacks 6212 |
| system.cpu.l2cache.WritebackClean_hits::total 6212 |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 16 |
| system.cpu.l2cache.ReadExReq_hits::total 16 |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 |
| system.cpu.l2cache.ReadCleanReq_hits::total 12995 |
| system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 |
| system.cpu.l2cache.ReadSharedReq_hits::total 238 |
| system.cpu.l2cache.demand_hits::cpu.inst 12995 |
| system.cpu.l2cache.demand_hits::cpu.data 254 |
| system.cpu.l2cache.demand_hits::total 13249 |
| system.cpu.l2cache.overall_hits::cpu.inst 12995 |
| system.cpu.l2cache.overall_hits::cpu.data 254 |
| system.cpu.l2cache.overall_hits::total 13249 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 |
| system.cpu.l2cache.ReadExReq_misses::total 2856 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 |
| system.cpu.l2cache.ReadCleanReq_misses::total 2608 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 |
| system.cpu.l2cache.ReadSharedReq_misses::total 1368 |
| system.cpu.l2cache.demand_misses::cpu.inst 2608 |
| system.cpu.l2cache.demand_misses::cpu.data 4224 |
| system.cpu.l2cache.demand_misses::total 6832 |
| system.cpu.l2cache.overall_misses::cpu.inst 2608 |
| system.cpu.l2cache.overall_misses::cpu.data 4224 |
| system.cpu.l2cache.overall_misses::total 6832 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 |
| system.cpu.l2cache.demand_miss_latency::total 413785500 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 |
| system.cpu.l2cache.overall_miss_latency::total 413785500 |
| system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 |
| system.cpu.l2cache.WritebackDirty_accesses::total 998 |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 |
| system.cpu.l2cache.WritebackClean_accesses::total 6212 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 |
| system.cpu.l2cache.ReadExReq_accesses::total 2872 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 15603 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 1606 |
| system.cpu.l2cache.demand_accesses::cpu.inst 15603 |
| system.cpu.l2cache.demand_accesses::cpu.data 4478 |
| system.cpu.l2cache.demand_accesses::total 20081 |
| system.cpu.l2cache.overall_accesses::cpu.inst 15603 |
| system.cpu.l2cache.overall_accesses::cpu.data 4478 |
| system.cpu.l2cache.overall_accesses::total 20081 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 |
| system.cpu.l2cache.demand_miss_rate::total 0.340222 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 |
| system.cpu.l2cache.overall_miss_rate::total 0.340222 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 |
| system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 |
| system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 |
| system.cpu.l2cache.demand_mshr_misses::total 6832 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 |
| system.cpu.l2cache.overall_mshr_misses::total 6832 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 35209 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 17209 |
| system.cpu.toL2Bus.trans_dist::WritebackDirty 998 |
| system.cpu.toL2Bus.trans_dist::WritebackClean 13796 |
| system.cpu.toL2Bus.trans_dist::CleanEvict 334 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 2872 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 2872 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 |
| system.cpu.toL2Bus.pkt_count::total 55290 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 |
| system.cpu.toL2Bus.pkt_size::total 2232000 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 20081 |
| system.cpu.toL2Bus.snoop_fanout::mean 0.386335 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% |
| system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 |
| system.cpu.toL2Bus.snoop_fanout::total 20081 |
| system.cpu.toL2Bus.reqLayer0.occupancy 32398500 |
| system.cpu.toL2Bus.reqLayer0.utilization 0.0 |
| system.cpu.toL2Bus.respLayer0.occupancy 23404500 |
| system.cpu.toL2Bus.respLayer0.utilization 0.0 |
| system.cpu.toL2Bus.respLayer1.occupancy 6717000 |
| system.cpu.toL2Bus.respLayer1.utilization 0.0 |
| system.membus.snoop_filter.tot_requests 6833 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 |
| system.membus.trans_dist::ReadResp 3976 |
| system.membus.trans_dist::ReadExReq 2856 |
| system.membus.trans_dist::ReadExResp 2856 |
| system.membus.trans_dist::ReadSharedReq 3976 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 |
| system.membus.pkt_count::total 13664 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 |
| system.membus.pkt_size::total 437248 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 6833 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 6833 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 6833 |
| system.membus.reqLayer0.occupancy 7281500 |
| system.membus.reqLayer0.utilization 0.0 |
| system.membus.respLayer1.occupancy 34160000 |
| system.membus.respLayer1.utilization 0.0 |
| |
| ---------- End Simulation Statistics ---------- |
