tree 25cee99edad0da70e0bfb0975dd74a6b5b073f25
parent 5d45c50b480d6ff31c9a461c1b6d3d212ef5ff0e
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1651237579 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1651963272 +0000

system-arm: Fix GICv3 in multi-cluster configuration

Current way of initializing GICv3 in the gem5 bootloader doesn't
work when there is a PE labelled with non-zero Aff1, Aff2 or Aff3
in the MPIDR_EL1 register
(For example in a multi-cluster configuration).

This is because the bootloader is considering Aff0 only

mrs x0, mpidr_el1
// extract the primary CPU.
ldr x1, =0xff00ffffff
and    x2, x0, #0xff // use Aff0 as cpuid for now...

With this patch we are solving the issue, by considering
every affinity number. Now the primary cpu is the cpu with

Aff3..Aff0 = 0.

The bootloader was also using Aff0 (stored in x2, see above)
to let every CPU index their own redistributor memory mapped frames.
In this model every secondary CPU was in charge of initializing
their own redistributor registers.

This can't be used anymore as we have a tuple of affinity
numbers now rather than a single flat index.

We are addressing the issue by letting the primary cpu initialize
every redistributor in the system. This is done by iterating
over consecutive frames and by reading GICR_TYPER.Last, which
is set to 1 if the current frame is the last one.

Change-Id: I2bcad286c2282bf1c47618e5391bf1c2e2b27013
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59393
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>