diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh
index aa94942..709c944 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -92,7 +92,11 @@
     CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
         : RiscvStaticInst(mnem, _machInst, __opClass),
             csr(FUNCT12), uimm(CSRIMM)
-    {}
+    {
+        if (csr == CSR_SATP) {
+            flags[IsSquashAfter] = true;
+        }
+    }
 
     std::string generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const override;
diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index d36dc1d..15c5cf9 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -54,7 +54,7 @@
 PMAChecker::check(const RequestPtr &req)
 {
     if (isUncacheable(req->getPaddr(), req->getSize())) {
-        req->setFlags(Request::UNCACHEABLE);
+        req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
     }
 }
 
diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 641ba6f..ced9122 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -64,7 +64,9 @@
     for (int context_id = 0; context_id < nThread; context_id++) {
 
         // Update misc reg file
-        system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME, mtime);
+        ISA* isa = dynamic_cast<ISA*>(
+            system->threads[context_id]->getIsaPtr());
+        isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
 
         // Post timer interrupt
         uint64_t mtimecmp = registers.mtimecmp[context_id].get();