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/*
* Copyright 2020 Google Inc.
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* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_RISCV_SE_WORKLOAD_HH__
#define __ARCH_RISCV_SE_WORKLOAD_HH__
#include "arch/riscv/reg_abi.hh"
#include "arch/riscv/registers.hh"
#include "params/RiscvSEWorkload.hh"
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"
namespace RiscvISA
{
class SEWorkload : public ::SEWorkload
{
public:
using Params = RiscvSEWorkloadParams;
SEWorkload(const Params &p) : ::SEWorkload(p) {}
::Loader::Arch getArch() const override { return ::Loader::Riscv64; }
//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
using SyscallABI = RegABI64;
};
} // namespace RiscvISA
namespace GuestABI
{
template <>
struct Result<RiscvISA::SEWorkload::SyscallABI, SyscallReturn>
{
static void
store(ThreadContext *tc, const SyscallReturn &ret)
{
if (ret.suppressed() || ret.needsRetry())
return;
if (ret.successful()) {
// no error
tc->setIntReg(RiscvISA::ReturnValueReg, ret.returnValue());
} else {
// got an error, return details
tc->setIntReg(RiscvISA::ReturnValueReg, ret.encodedValue());
}
}
};
} // namespace GuestABI
#endif // __ARCH_RISCV_SE_WORKLOAD_HH__