commit 47aa52ed17d4743909b7e63a59274a13a9361c66
author Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Sep 17 16:46:27 2020 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Sep 22 08:17:28 2020 +0000
tree 64e77a214bac41cac96d7c726a6b4a16f400d72b
parent b3719766f5567514a6b44d933228be4c255ee388

arch-arm: TLBI ALLE2IS should broadcast to the IS domain

This was implemented as a normal ALLE2 hence affecting the
current PE only

Change-Id: Ib369dd5a4b738daf96a01b5535d7481a97bb3730
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34795
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa.cc

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9ace236..cfef0ab 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1711,9 +1711,8 @@
                 tlbiOp.broadcast(tc);
                 return;
             }
-          // AArch64 TLB Invalidate All, EL2, Inner Shareable
+          // AArch64 TLB Invalidate All, EL2
           case MISCREG_TLBI_ALLE2:
-          case MISCREG_TLBI_ALLE2IS:
             {
                 assert64();
                 scr = readMiscReg(MISCREG_SCR);
@@ -1722,6 +1721,16 @@
                 tlbiOp(tc);
                 return;
             }
+          // AArch64 TLB Invalidate All, EL2, Inner Shareable
+          case MISCREG_TLBI_ALLE2IS:
+            {
+                assert64();
+                scr = readMiscReg(MISCREG_SCR);
+
+                TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
+                tlbiOp.broadcast(tc);
+                return;
+            }
           // AArch64 TLB Invalidate All, EL1
           case MISCREG_TLBI_ALLE1:
           case MISCREG_TLBI_VMALLS12E1: