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# -*- mode:python -*-
# Copyright (c) 2020-2021 Arm Limited
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#
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# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
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# this software without specific prior written permission.
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from m5.objects.ArmSystem import ArmRelease
from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB
from m5.objects.BaseMMU import BaseMMU
from m5.objects.ClockedObject import ClockedObject
from m5.params import *
from m5.proxy import *
# Basic stage 1 translation objects
class ArmTableWalker(ClockedObject):
type = 'ArmTableWalker'
cxx_class = 'gem5::ArmISA::TableWalker'
cxx_header = "arch/arm/table_walker.hh"
is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
num_squash_per_cycle = Param.Unsigned(2,
"Number of outstanding walks that can be squashed per cycle")
port = RequestPort("Table Walker port")
sys = Param.System(Parent.any, "system object parameter")
# Stage 2 translation objects, only used when virtualisation is being used
class ArmStage2TableWalker(ArmTableWalker):
is_stage2 = True
class ArmMMU(BaseMMU):
type = 'ArmMMU'
cxx_class = 'gem5::ArmISA::MMU'
cxx_header = 'arch/arm/mmu.hh'
# L2 TLBs
l2_shared = ArmTLB(entry_type="unified", size=1280)
# L1 TLBs
itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)
dtb = ArmTLB(entry_type="data", next_level=Parent.l2_shared)
stage2_itb = Param.ArmTLB(
ArmStage2TLB(entry_type="instruction"),
"Stage 2 Instruction TLB")
stage2_dtb = Param.ArmTLB(
ArmStage2TLB(entry_type="data"),
"Stage 2 Data TLB")
itb_walker = Param.ArmTableWalker(
ArmTableWalker(), "HW Table walker")
dtb_walker = Param.ArmTableWalker(
ArmTableWalker(), "HW Table walker")
stage2_itb_walker = Param.ArmTableWalker(
ArmStage2TableWalker(), "HW Table walker")
stage2_dtb_walker = Param.ArmTableWalker(
ArmStage2TableWalker(), "HW Table walker")
sys = Param.System(Parent.any, "system object parameter")
release_se = Param.ArmRelease(Parent.isa[0].release_se,
"Set of features/extensions to use in SE mode")
@classmethod
def walkerPorts(cls):
return ["mmu.itb_walker.port", "mmu.dtb_walker.port",
"mmu.stage2_itb_walker.port", "mmu.stage2_dtb_walker.port"]
def connectWalkerPorts(self, iport, dport):
self.itb_walker.port = iport
self.dtb_walker.port = dport
self.stage2_itb_walker.port = iport
self.stage2_dtb_walker.port = dport