)]}'
{
  "commit": "4dccd7dd6c69971541be2cbb0de4a2fe2b52f3ac",
  "tree": "f0737bedac38fb3505e9dbf2703a91af9c4afcf7",
  "parents": [
    "1a2904e021671374d20527b46a10d2de2ae310ce"
  ],
  "author": {
    "name": "Roger Chang",
    "email": "rogerycchang@google.com",
    "time": "Sat May 13 21:42:39 2023 +0800"
  },
  "committer": {
    "name": "Roger Chang",
    "email": "rogerycchang@google.com",
    "time": "Tue May 23 23:58:16 2023 +0000"
  },
  "message": "arch-riscv: Add BS format isa\n\nThis format is helper for aes32dsi, aes32dsmi, aes32esi, aes32esmi,\nsm4ed, sm4ks disassembly\n\nChange-Id: Ieff1932e267efc0a8c5fd8e557fc467dc376da4e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70598\nReviewed-by: Yu-hsin Wang \u003cyuhsingw@google.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n",
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