tree 0f2027b6d6257ea3f5e9434e00b8088d1f653363
parent 8a78358a3064251f51f8bf0b323330efe60a70b2
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1666352216 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1666884798 +0000

dev-arm: Use ThreadContext instead if ISA in GICV3 cpu interface

Some CPU wrappers like the Fastmodel one do extend the
ThreadContext interface in order to retrieve system register
state... By bypassing the TC interface and by using the ISA
instead, we are basically forcing users to extend the ISA
as well to intercept these calls.

So with this patch we are making sure every system register is accessed
(like HCR_EL2 or SCR_EL3) through the thread context. This of course
does not apply to the CPU interface registers as we still use the ISA
storage for them.  In the future we should probably move that storage
from the ISA class to the Gicv3CPUInterface class itself

This is also simplifying Gicv3CPUInterface::isEL3OrMon:
currEL already covers the AArch32 case so no need to
differentiate between AArch32 and AArch64

Change-Id: I446a14a6e12b77e1a62040b3422f79ae52cc9eec
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64913
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>