mem-ruby: Remove assertion with incorrect assumption
Current code assumes that only one cacheline would either be in
RW. This is not true for GPU protocols, and may not be true
for some CPU-only protocols with state violations.
Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc
index 572f5fe..83fa4c7 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -432,7 +432,6 @@
access_perm == AccessPermission_NotPresent)
num_invalid++;
}
- assert(num_rw <= 1);
// This if case is meant to capture what happens in a Broadcast/Snoop
// protocol where the block does not exist in the cache hierarchy. You
@@ -451,7 +450,14 @@
return true;
}
}
- } else if (num_ro > 0 || num_rw == 1) {
+ } else if (num_ro > 0 || num_rw >= 1) {
+ if (num_rw > 1) {
+ // We iterate over the vector of abstract controllers, and return
+ // the first copy found. If we have more than one cache with block
+ // in writable permission, the first one found would be returned.
+ warn("More than one Abstract Controller with RW permission for "
+ "addr: %#x on cacheline: %#x.", address, line_address);
+ }
// In Broadcast/Snoop protocols, this covers if you know the block
// exists somewhere in the caching hierarchy, then you want to read any
// valid RO or RW block. In directory protocols, same thing, you want
