tree c85ab6abc19959235d5cd6b184cbae298755fd63
parent 7bd5f554b53ee8763fd20e2cd214539d3ec93158
author Pouya Fotouhi <Pouya.Fotouhi@amd.com> 1564514513 -0500
committer Anthony Gutierrez <anthony.gutierrez@amd.com> 1564770672 +0000

mem-ruby: Remove assertion with incorrect assumption

Current code assumes that only one cacheline would either be in
RW. This is not true for GPU protocols, and may not be true
for some CPU-only protocols with state violations.

Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>