src/mem/ruby/protocol/MESI_Three_Level-msg.sm

/*
 * Copyright (c) 2020 ARM Limited
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 * to a hardware implementation of the functionality of the software
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 *
 * Copyright (c) 2013 Mark D. Hill and David A. Wood
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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// Various class of messages that can be exchanged between the L0 and the L1
// controllers.
enumeration(CoherenceClass, desc="...") {
  GETX,      desc="Get eXclusive";
  UPGRADE,   desc="UPGRADE to exclusive";
  GETS,      desc="Get Shared";
  GET_INSTR, desc="Get Instruction";
  INV_OWN,   desc="Invalidate (own)";
  INV_ELSE,  desc="Invalidate (else)";
  PUTX,      desc="Replacement message";
  PUTX_COPY, desc="Data block to be copied in L1. L0 will still be in M state";

  WB_ACK,    desc="Writeback ack";

  // Request types for sending data and acks from L0 to L1 cache
  // when an invalidation message is received.
  INV_DATA;
  INV_ACK;

  DATA, desc="Data block for L1 cache in S state";
  DATA_EXCLUSIVE, desc="Data block for L1 cache in M/E state";
  ACK, desc="Generic invalidate ack";
  NAK, desc="Used by L0 to tell L1 that it cannot provide the latest value";

  // This is a special case in which the L1 cache lost permissions to the
  // shared block before it got the data. So the L0 cache can use the data
  // but not store it.
  STALE_DATA;
}

// Class for messages sent between the L0 and the L1 controllers.
structure(CoherenceMsg, desc="...", interface="Message") {
  Addr addr,              desc="Physical address of the cache block";
  CoherenceClass Class,         desc="Type of message (GetS, GetX, PutX, etc)";
  RubyAccessMode AccessMode,    desc="user/supervisor access type";
  MachineID Sender,             desc="What component sent this message";
  MachineID Dest,        desc="What machine receives this message";
  MessageSizeType MessageSize,  desc="size category of the message";
  DataBlock DataBlk,            desc="Data for the cache line (if PUTX)";
  bool Dirty, default="false",  desc="Dirty bit";
  PrefetchBit Prefetch,         desc="Is this a prefetch request";

  bool functionalRead(Packet *pkt) {
    // Only PUTX messages contains the data block
    if (Class == CoherenceClass:PUTX) {
        return testAndRead(addr, DataBlk, pkt);
    }

    return false;
  }

  bool functionalWrite(Packet *pkt) {
    // No check on message type required since the protocol should
    // read data from those messages that contain the block
    return testAndWrite(addr, DataBlk, pkt);
  }
}