diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4e36d55..cc86752 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -112,6 +112,8 @@
 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
 {
     switch (misc_reg) {
+      case MISCREG_HARTID:
+        return tc->contextId();
       case MISCREG_CYCLE:
         if (hpmCounterEnabled(MISCREG_CYCLE)) {
             DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",