src/arch/riscv/pma_checker.hh

/*
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#ifndef __ARCH_RISCV_PMA_CHECKER_HH__
#define __ARCH_RISCV_PMA_CHECKER_HH__

#include "base/addr_range.hh"
#include "base/types.hh"
#include "mem/packet.hh"
#include "params/PMAChecker.hh"
#include "sim/sim_object.hh"

namespace gem5
{

/**
 * Based on the RISC-V ISA privileged specifications
 * V1.11, there is no implementation guidelines on the
 * Physical Memory Attributes.
 *
 * This class provides an abstract PMAChecker for RISC-V
 * to provide PMA checking functionality. However,
 * hardware latencies are not modelled.
 */

class PMAChecker : public SimObject
{
  public:

    typedef PMACheckerParams Params;

    const Params &
    params() const
    {
        return dynamic_cast<const Params &>(_params);
    }
    PMAChecker(const Params &params);

    AddrRangeList uncacheable;

    void check(const RequestPtr &req);

    bool isUncacheable(const AddrRange &range);
    bool isUncacheable(const Addr &addr, const unsigned size);
    bool isUncacheable(PacketPtr pkt);

    void takeOverFrom(PMAChecker *old);
};

} // namespace gem5

#endif // __ARCH_RISCV_PMA_CHECKER_HH__